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| author | johpow01 <john.powell@arm.com> | 2021-08-04 19:38:18 -0500 |
|---|---|---|
| committer | John <john.powell@arm.com> | 2021-09-27 17:07:52 +0200 |
| commit | cb4ec47b5c73e04472984acf821e6be41b98064f (patch) | |
| tree | 2489a386867098d385fdf263dc8cc1bcd2f98a4a /include/arch/aarch64/arch.h | |
| parent | c7c22ab662008ca6cfb8b1926bbaa5fdc8eb399e (diff) | |
| download | arm-trusted-firmware-cb4ec47b5c73e04472984acf821e6be41b98064f.tar.gz | |
feat(hcx): add build option to enable FEAT_HCX
FEAT_HCX adds the extended hypervisor configuration register (HCRX_EL2)
and access to this register must be explicitly enabled through the
SCR_EL3.HXEn bit. This patch adds a new build flag ENABLE_FEAT_HCX to
allow the register to be accessed from EL2.
Signed-off-by: John Powell <john.powell@arm.com>
Change-Id: Ibb36ad90622f1dc857adab4b0d4d7a89456a522b
Diffstat (limited to 'include/arch/aarch64/arch.h')
| -rw-r--r-- | include/arch/aarch64/arch.h | 16 |
1 files changed, 16 insertions, 0 deletions
diff --git a/include/arch/aarch64/arch.h b/include/arch/aarch64/arch.h index 9ea111452..d260ecf45 100644 --- a/include/arch/aarch64/arch.h +++ b/include/arch/aarch64/arch.h @@ -281,6 +281,11 @@ #define ID_AA64MMFR1_EL1_VHE_SHIFT U(8) #define ID_AA64MMFR1_EL1_VHE_MASK ULL(0xf) +#define ID_AA64MMFR1_EL1_HCX_SHIFT U(40) +#define ID_AA64MMFR1_EL1_HCX_MASK ULL(0xf) +#define ID_AA64MMFR1_EL1_HCX_SUPPORTED ULL(0x1) +#define ID_AA64MMFR1_EL1_HCX_NOT_SUPPORTED ULL(0x0) + /* ID_AA64MMFR2_EL1 definitions */ #define ID_AA64MMFR2_EL1 S3_0_C0_C7_2 @@ -429,6 +434,7 @@ #define SCR_RES1_BITS ((U(1) << 4) | (U(1) << 5)) #define SCR_TWEDEL_SHIFT U(30) #define SCR_TWEDEL_MASK ULL(0xf) +#define SCR_HXEn_BIT (UL(1) << 38) #define SCR_AMVOFFEN_BIT (UL(1) << 35) #define SCR_TWEDEn_BIT (UL(1) << 29) #define SCR_ECVEN_BIT (UL(1) << 28) @@ -1144,6 +1150,16 @@ #define GCR_EL1 S3_0_C1_C0_6 /******************************************************************************* + * FEAT_HCX - Extended Hypervisor Configuration Register + ******************************************************************************/ +#define HCRX_EL2 S3_4_C1_C2_2 +#define HCRX_EL2_FGTnXS_BIT (UL(1) << 4) +#define HCRX_EL2_FnXS_BIT (UL(1) << 3) +#define HCRX_EL2_EnASR_BIT (UL(1) << 2) +#define HCRX_EL2_EnALS_BIT (UL(1) << 1) +#define HCRX_EL2_EnAS0_BIT (UL(1) << 0) + +/******************************************************************************* * Definitions for DynamicIQ Shared Unit registers ******************************************************************************/ #define CLUSTERPWRDN_EL1 S3_0_c15_c3_6 |