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| author | Tomas Pilar <tomas@nuviainc.com> | 2020-10-28 15:34:12 +0000 |
|---|---|---|
| committer | Tomas Pilar <tomas@nuviainc.com> | 2021-01-15 15:18:02 +0000 |
| commit | 7c802c715f14b203e5dfc7e4ccee498b861eb406 (patch) | |
| tree | dd7f628c3c0cb48847aff61166b046a8d335b677 /include/arch/aarch64/arch.h | |
| parent | 337e493306cbeda2b3e5c10f681607c7aea8bbb4 (diff) | |
| download | arm-trusted-firmware-7c802c715f14b203e5dfc7e4ccee498b861eb406.tar.gz | |
Define registers for FEAT_RNG support
Add ISAR0 feature register read helper, location
of FEAT_RNG bits, feature support helper and the
rndr/rndrrs register read helpers.
Signed-off-by: Tomas Pilar <tomas@nuviainc.com>
Change-Id: I2a785a36f62a917548e55892ce92fa8b72fcb99d
Diffstat (limited to 'include/arch/aarch64/arch.h')
| -rw-r--r-- | include/arch/aarch64/arch.h | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/include/arch/aarch64/arch.h b/include/arch/aarch64/arch.h index 09e598a2d..2cdc7b230 100644 --- a/include/arch/aarch64/arch.h +++ b/include/arch/aarch64/arch.h @@ -193,6 +193,10 @@ #define ID_AA64DFR0_MTPMU_MASK ULL(0xf) #define ID_AA64DFR0_MTPMU_SUPPORTED ULL(1) +/* ID_AA64ISAR0_EL1 definitions */ +#define ID_AA64ISAR0_RNDR_SHIFT U(60) +#define ID_AA64ISAR0_RNDR_MASK ULL(0xf) + /* ID_AA64ISAR1_EL1 definitions */ #define ID_AA64ISAR1_EL1 S3_0_C0_C6_1 #define ID_AA64ISAR1_GPI_SHIFT U(28) |