diff options
| author | Chris Kay <chris.kay@arm.com> | 2021-05-26 11:58:23 +0100 |
|---|---|---|
| committer | Chris Kay <chris.kay@arm.com> | 2021-10-26 12:14:31 +0100 |
| commit | 33b9be6d758d4fcef1f5a9802a54bb56f2c4ff8d (patch) | |
| tree | a871400cbc2c690cfbd292438012a26adcfcb3ba /include/arch/aarch64/arch.h | |
| parent | b4b726ea868359cf683c07337b69fe91a2a6929a (diff) | |
| download | arm-trusted-firmware-33b9be6d758d4fcef1f5a9802a54bb56f2c4ff8d.tar.gz | |
refactor(amu): factor out register accesses
This change introduces a small set of register getters and setters to
avoid having to repeatedly mask and shift in complex code.
Change-Id: Ia372f60c5efb924cd6eeceb75112e635ad13d942
Signed-off-by: Chris Kay <chris.kay@arm.com>
Diffstat (limited to 'include/arch/aarch64/arch.h')
| -rw-r--r-- | include/arch/aarch64/arch.h | 28 |
1 files changed, 24 insertions, 4 deletions
diff --git a/include/arch/aarch64/arch.h b/include/arch/aarch64/arch.h index 74bc8cb8a..a72087e8f 100644 --- a/include/arch/aarch64/arch.h +++ b/include/arch/aarch64/arch.h @@ -532,7 +532,8 @@ /* HCR definitions */ #define HCR_RESET_VAL ULL(0x0) -#define HCR_AMVOFFEN_BIT (ULL(1) << 51) +#define HCR_AMVOFFEN_SHIFT U(51) +#define HCR_AMVOFFEN_BIT (ULL(1) << HCR_AMVOFFEN_SHIFT) #define HCR_TEA_BIT (ULL(1) << 47) #define HCR_API_BIT (ULL(1) << 41) #define HCR_APK_BIT (ULL(1) << 40) @@ -570,7 +571,8 @@ /* CPTR_EL3 definitions */ #define TCPAC_BIT (U(1) << 31) -#define TAM_BIT (U(1) << 30) +#define TAM_SHIFT U(30) +#define TAM_BIT (U(1) << TAM_SHIFT) #define TTA_BIT (U(1) << 20) #define TFP_BIT (U(1) << 10) #define CPTR_EZ_BIT (U(1) << 8) @@ -579,7 +581,8 @@ /* CPTR_EL2 definitions */ #define CPTR_EL2_RES1 ((U(1) << 13) | (U(1) << 12) | (U(0x3ff))) #define CPTR_EL2_TCPAC_BIT (U(1) << 31) -#define CPTR_EL2_TAM_BIT (U(1) << 30) +#define CPTR_EL2_TAM_SHIFT U(30) +#define CPTR_EL2_TAM_BIT (U(1) << CPTR_EL2_TAM_SHIFT) #define CPTR_EL2_TTA_BIT (U(1) << 20) #define CPTR_EL2_TFP_BIT (U(1) << 10) #define CPTR_EL2_TZ_BIT (U(1) << 8) @@ -1043,6 +1046,22 @@ #define AMEVTYPER1E_EL0 S3_3_C13_C15_6 #define AMEVTYPER1F_EL0 S3_3_C13_C15_7 +/* AMCNTENSET0_EL0 definitions */ +#define AMCNTENSET0_EL0_Pn_SHIFT U(0) +#define AMCNTENSET0_EL0_Pn_MASK ULL(0xffff) + +/* AMCNTENSET1_EL0 definitions */ +#define AMCNTENSET1_EL0_Pn_SHIFT U(0) +#define AMCNTENSET1_EL0_Pn_MASK ULL(0xffff) + +/* AMCNTENCLR0_EL0 definitions */ +#define AMCNTENCLR0_EL0_Pn_SHIFT U(0) +#define AMCNTENCLR0_EL0_Pn_MASK ULL(0xffff) + +/* AMCNTENCLR1_EL0 definitions */ +#define AMCNTENCLR1_EL0_Pn_SHIFT U(0) +#define AMCNTENCLR1_EL0_Pn_MASK ULL(0xffff) + /* AMCFGR_EL0 definitions */ #define AMCFGR_EL0_NCG_SHIFT U(28) #define AMCFGR_EL0_NCG_MASK U(0xf) @@ -1074,7 +1093,8 @@ #define AMCG1IDR_VOFF_SHIFT U(16) /* New bit added to AMCR_EL0 */ -#define AMCR_CG1RZ_BIT (ULL(0x1) << 17) +#define AMCR_CG1RZ_SHIFT U(17) +#define AMCR_CG1RZ_BIT (ULL(0x1) << AMCR_CG1RZ_SHIFT) /* * Definitions for virtual offset registers for architected activity monitor |