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| author | Mark Brown <broonie@kernel.org> | 2023-03-14 20:48:43 +0000 |
|---|---|---|
| committer | Mark Brown <broonie@kernel.org> | 2023-04-12 15:03:22 +0100 |
| commit | 062b6c6bf23f9656332b0aa3fed59c15f34f9361 (patch) | |
| tree | 74d6d9a353e253cc539d7d47a5c6c85d70e17a0a /include/arch/aarch64/arch.h | |
| parent | 2237e562fd4d68cf4051e51bbff33ebd9ad14ae2 (diff) | |
| download | arm-trusted-firmware-062b6c6bf23f9656332b0aa3fed59c15f34f9361.tar.gz | |
feat(pie/por): support permission indirection and overlay
Arm v8.9 introduces a series of features providing a new way to set memory
permissions. Instead of directly encoding the permissions in the page
tables the PTEs contain indexes into an array of permissions stored in
system registers, allowing greater flexibility and density of encoding.
Enable access to these features for EL2 and below, context switching the
newly added EL2 registers as appropriate. Since all of FEAT_S[12]P[IO]E
are separately discoverable we have separate build time options for
enabling them, but note that there is overlap in the registers that they
implement and the enable bit required for lower EL access.
Change the FVP platform to default to handling them as dynamic options so
the right decision can be made by the code at runtime.
Signed-off-by: Mark Brown <broonie@kernel.org>
Change-Id: Icf89e444e39e1af768739668b505661df18fb234
Diffstat (limited to 'include/arch/aarch64/arch.h')
| -rw-r--r-- | include/arch/aarch64/arch.h | 22 |
1 files changed, 22 insertions, 0 deletions
diff --git a/include/arch/aarch64/arch.h b/include/arch/aarch64/arch.h index dee7fdcff..9b55658ff 100644 --- a/include/arch/aarch64/arch.h +++ b/include/arch/aarch64/arch.h @@ -355,6 +355,18 @@ /* ID_AA64MMFR3_EL1 definitions */ #define ID_AA64MMFR3_EL1 S3_0_C0_C7_3 +#define ID_AA64MMFR3_EL1_S2POE_SHIFT U(20) +#define ID_AA64MMFR3_EL1_S2POE_MASK ULL(0xf) + +#define ID_AA64MMFR3_EL1_S1POE_SHIFT U(16) +#define ID_AA64MMFR3_EL1_S1POE_MASK ULL(0xf) + +#define ID_AA64MMFR3_EL1_S2PIE_SHIFT U(12) +#define ID_AA64MMFR3_EL1_S2PIE_MASK ULL(0xf) + +#define ID_AA64MMFR3_EL1_S1PIE_SHIFT U(8) +#define ID_AA64MMFR3_EL1_S1PIE_MASK ULL(0xf) + #define ID_AA64MMFR3_EL1_TCRX_SHIFT U(0) #define ID_AA64MMFR3_EL1_TCRX_MASK ULL(0xf) @@ -512,6 +524,7 @@ #define SCR_GPF_BIT (UL(1) << 48) #define SCR_TWEDEL_SHIFT U(30) #define SCR_TWEDEL_MASK ULL(0xf) +#define SCR_PIEN_BIT (UL(1) << 45) #define SCR_TCR2EN_BIT (UL(1) << 43) #define SCR_TRNDR_BIT (UL(1) << 40) #define SCR_HXEn_BIT (UL(1) << 38) @@ -1321,6 +1334,15 @@ #define TCR2_EL2 S3_4_C2_C0_3 /******************************************************************************* + * Permission indirection and overlay + ******************************************************************************/ + +#define PIRE0_EL2 S3_4_C10_C2_2 +#define PIR_EL2 S3_4_C10_C2_3 +#define POR_EL2 S3_4_C10_C2_4 +#define S2PIR_EL2 S3_4_C10_C2_5 + +/******************************************************************************* * Definitions for DynamicIQ Shared Unit registers ******************************************************************************/ #define CLUSTERPWRDN_EL1 S3_0_c15_c3_6 |