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| author | Jayanth Dodderi Chidanand <jayanthdodderi.chidanand@arm.com> | 2022-11-08 10:31:07 +0000 |
|---|---|---|
| committer | Jayanth Dodderi Chidanand <jayanthdodderi.chidanand@arm.com> | 2023-04-27 16:02:27 +0100 |
| commit | 03d3c0d729e24713d657209bedf74d255550babb (patch) | |
| tree | 5e85a68857537809756ef9521e221effc0a7725f /include/arch/aarch64/arch.h | |
| parent | d5f19c49baa7f420daf3afa2b79cc977ce2e9c74 (diff) | |
| download | arm-trusted-firmware-03d3c0d729e24713d657209bedf74d255550babb.tar.gz | |
feat(sme): enable SME2 functionality for NS world
FEAT_SME2 is an extension of FEAT_SME and an optional feature
from v9.2. Its an extension of SME, wherein it not only
processes matrix operations efficiently, but also provides
outer-product instructions to accelerate matrix operations.
It affords instructions for multi-vector operations.
Further, it adds an 512 bit architectural register ZT0.
This patch implements all the changes introduced with FEAT_SME2
to ensure that the instructions are allowed to access ZT0
register from Non-secure lower exception levels.
Additionally, it adds support to ensure FEAT_SME2 is aligned
with the existing FEATURE DETECTION mechanism, and documented.
Change-Id: Iee0f61943304a9cfc3db8f986047b1321d0a6463
Signed-off-by: Jayanth Dodderi Chidanand <jayanthdodderi.chidanand@arm.com>
Diffstat (limited to 'include/arch/aarch64/arch.h')
| -rw-r--r-- | include/arch/aarch64/arch.h | 10 |
1 files changed, 9 insertions, 1 deletions
diff --git a/include/arch/aarch64/arch.h b/include/arch/aarch64/arch.h index 9e061bfb4..ac5eae249 100644 --- a/include/arch/aarch64/arch.h +++ b/include/arch/aarch64/arch.h @@ -412,6 +412,7 @@ #define ID_AA64PFR1_EL1_SME_MASK ULL(0xf) #define ID_AA64PFR1_EL1_SME_NOT_SUPPORTED ULL(0x0) #define ID_AA64PFR1_EL1_SME_SUPPORTED ULL(0x1) +#define ID_AA64PFR1_EL1_SME2_SUPPORTED ULL(0x2) /* ID_PFR1_EL1 definitions */ #define ID_PFR1_VIRTEXT_SHIFT U(12) @@ -519,6 +520,8 @@ #define CPACR_EL1_FP_TRAP_EL0 UL(0x1) #define CPACR_EL1_FP_TRAP_ALL UL(0x2) #define CPACR_EL1_FP_TRAP_NONE UL(0x3) +#define CPACR_EL1_SMEN_SHIFT U(24) +#define CPACR_EL1_SMEN_MASK ULL(0x3) /* SCR definitions */ #define SCR_RES1_BITS ((U(1) << 4) | (U(1) << 5)) @@ -1026,11 +1029,16 @@ #define ID_AA64SMFR0_EL1_SME_FA64_SHIFT U(63) #define ID_AA64SMFR0_EL1_SME_FA64_MASK U(0x1) #define ID_AA64SMFR0_EL1_SME_FA64_SUPPORTED U(0x1) +#define ID_AA64SMFR0_EL1_SME_VER_SHIFT U(55) +#define ID_AA64SMFR0_EL1_SME_VER_MASK ULL(0xf) +#define ID_AA64SMFR0_EL1_SME_INST_SUPPORTED ULL(0x0) +#define ID_AA64SMFR0_EL1_SME2_INST_SUPPORTED ULL(0x1) /* SMCR_ELx definitions */ #define SMCR_ELX_LEN_SHIFT U(0) -#define SMCR_ELX_LEN_MASK U(0x1ff) +#define SMCR_ELX_LEN_MAX U(0x1ff) #define SMCR_ELX_FA64_BIT (U(1) << 31) +#define SMCR_ELX_EZT0_BIT (U(1) << 30) /******************************************************************************* * Definitions of MAIR encodings for device and normal memory |