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| author | Madhukar Pappireddy <madhukar.pappireddy@arm.com> | 2022-09-07 15:38:06 +0200 |
|---|---|---|
| committer | TrustedFirmware Code Review <review@review.trustedfirmware.org> | 2022-09-07 15:38:06 +0200 |
| commit | 8a858913b10d5f5032920892bc6b278cf7117f4d (patch) | |
| tree | 2966a684312923a090303a51b924df7204800dfd /fdts | |
| parent | f1f2384b3b0d051be18635c7f40b268ba5800358 (diff) | |
| parent | 5dbda5cb23016cea3f9a917a1b3a18c05fbc3403 (diff) | |
| download | arm-trusted-firmware-8a858913b10d5f5032920892bc6b278cf7117f4d.tar.gz | |
Merge changes from topic "stm32mp15-dt-updates" into integration
* changes:
refactor(stm32mp15-fdts): remove timers15 node
refactor(stm32mp15-fdts): remove unused secure-status properties
refactor(stm32mp15-fdts): remove RCC secure-status
Diffstat (limited to 'fdts')
| -rw-r--r-- | fdts/stm32mp157a-avenger96.dts | 2 | ||||
| -rw-r--r-- | fdts/stm32mp157c-ed1.dts | 1 | ||||
| -rw-r--r-- | fdts/stm32mp157c-odyssey-som.dtsi | 1 | ||||
| -rw-r--r-- | fdts/stm32mp15xx-dhcom-som.dtsi | 2 | ||||
| -rw-r--r-- | fdts/stm32mp15xx-dhcor-som.dtsi | 2 | ||||
| -rw-r--r-- | fdts/stm32mp15xx-dkx.dtsi | 6 | ||||
| -rw-r--r-- | fdts/stm32mp15xx-osd32.dtsi | 1 |
7 files changed, 0 insertions, 15 deletions
diff --git a/fdts/stm32mp157a-avenger96.dts b/fdts/stm32mp157a-avenger96.dts index 6ae97c758..f0da350bb 100644 --- a/fdts/stm32mp157a-avenger96.dts +++ b/fdts/stm32mp157a-avenger96.dts @@ -163,7 +163,6 @@ &iwdg2 { timeout-sec = <32>; status = "okay"; - secure-status = "okay"; }; &pwr_regulators { @@ -172,7 +171,6 @@ }; &rcc { - secure-status = "disabled"; st,clksrc = < CLK_MPU_PLL1P CLK_AXI_PLL2P diff --git a/fdts/stm32mp157c-ed1.dts b/fdts/stm32mp157c-ed1.dts index 659e8bf85..d9285638a 100644 --- a/fdts/stm32mp157c-ed1.dts +++ b/fdts/stm32mp157c-ed1.dts @@ -201,7 +201,6 @@ }; &rcc { - secure-status = "disabled"; st,clksrc = < CLK_MPU_PLL1P CLK_AXI_PLL2P diff --git a/fdts/stm32mp157c-odyssey-som.dtsi b/fdts/stm32mp157c-odyssey-som.dtsi index c4e13985a..091e327cf 100644 --- a/fdts/stm32mp157c-odyssey-som.dtsi +++ b/fdts/stm32mp157c-odyssey-som.dtsi @@ -203,7 +203,6 @@ }; &rcc { - secure-status = "disabled"; st,clksrc = < CLK_MPU_PLL1P CLK_AXI_PLL2P diff --git a/fdts/stm32mp15xx-dhcom-som.dtsi b/fdts/stm32mp15xx-dhcom-som.dtsi index 3021ef817..c9f21b0e6 100644 --- a/fdts/stm32mp15xx-dhcom-som.dtsi +++ b/fdts/stm32mp15xx-dhcom-som.dtsi @@ -160,7 +160,6 @@ &iwdg2 { timeout-sec = <32>; status = "okay"; - secure-status = "okay"; }; &pwr_regulators { @@ -187,7 +186,6 @@ }; &rcc { - secure-status = "disabled"; st,clksrc = < CLK_MPU_PLL1P CLK_AXI_PLL2P diff --git a/fdts/stm32mp15xx-dhcor-som.dtsi b/fdts/stm32mp15xx-dhcor-som.dtsi index 0774c1d37..c241efc48 100644 --- a/fdts/stm32mp15xx-dhcor-som.dtsi +++ b/fdts/stm32mp15xx-dhcor-som.dtsi @@ -155,7 +155,6 @@ &iwdg2 { timeout-sec = <32>; status = "okay"; - secure-status = "okay"; }; &pwr_regulators { @@ -182,7 +181,6 @@ }; &rcc { - secure-status = "disabled"; st,clksrc = < CLK_MPU_PLL1P CLK_AXI_PLL2P diff --git a/fdts/stm32mp15xx-dkx.dtsi b/fdts/stm32mp15xx-dkx.dtsi index 74e529d9d..52d4170fd 100644 --- a/fdts/stm32mp15xx-dkx.dtsi +++ b/fdts/stm32mp15xx-dkx.dtsi @@ -180,7 +180,6 @@ &iwdg2 { timeout-sec = <32>; status = "okay"; - secure-status = "okay"; }; &pwr_regulators { @@ -189,7 +188,6 @@ }; &rcc { - secure-status = "disabled"; st,clksrc = < CLK_MPU_PLL1P CLK_AXI_PLL2P @@ -304,10 +302,6 @@ status = "okay"; }; -&timers15 { - secure-status = "okay"; -}; - &uart4 { pinctrl-names = "default"; pinctrl-0 = <&uart4_pins_a>; diff --git a/fdts/stm32mp15xx-osd32.dtsi b/fdts/stm32mp15xx-osd32.dtsi index c7ddc92be..52a5d380b 100644 --- a/fdts/stm32mp15xx-osd32.dtsi +++ b/fdts/stm32mp15xx-osd32.dtsi @@ -181,7 +181,6 @@ /* CLOCK init */ &rcc { - secure-status = "disabled"; st,clksrc = < CLK_MPU_PLL1P CLK_AXI_PLL2P |