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| author | Marek Behún <marek.behun@nic.cz> | 2021-12-01 18:03:09 +0100 |
|---|---|---|
| committer | Marek Behún <marek.behun@nic.cz> | 2021-12-09 01:28:45 +0100 |
| commit | 4d01bfe66522b13f0d9042206e986551c94fc01e (patch) | |
| tree | df37e263db755f9fbf6807144277b97aec335639 /drivers/marvell/comphy | |
| parent | 71183ef6654c2a485458307a84ce7c473524689a (diff) | |
| download | arm-trusted-firmware-4d01bfe66522b13f0d9042206e986551c94fc01e.tar.gz | |
fix(drivers/marvell/comphy-3700): use reg_set() according to update semantics
Currently reg_set() and reg_set16() are almost everywhere (both in
phy-comphy-3700.c and phy-comphy-cp110.c) used as if the semantics were
that of register update function (only bits that are set in mask are
updated):
reg_set(addr, data, mask) {
*addr = (*addr & ~mask) | (data & mask);
}
This comes both from names of arguments (data and mask), and from usage.
But both functions are in fact implemented via mmio_clrsetbits_32(), so
they actually first clear bits from mask and then set bits from data:
reg_set(addr, data, mask) {
*addr = (*addr & ~mask) | data;
}
There are only two places where this is leveraged (where some bits are
put into data argument but they are not put into the mask argument).
Fix those two usages to allow to convert the implementation from
clrsetbits semantics to update semantics.
Signed-off-by: Marek Behún <marek.behun@nic.cz>
Change-Id: Ib29a1dd7edcdee7a39c4752dbc9dfcd600d8cb5c
Diffstat (limited to 'drivers/marvell/comphy')
| -rw-r--r-- | drivers/marvell/comphy/phy-comphy-3700.c | 8 |
1 files changed, 4 insertions, 4 deletions
diff --git a/drivers/marvell/comphy/phy-comphy-3700.c b/drivers/marvell/comphy/phy-comphy-3700.c index 4dfe05679..069564586 100644 --- a/drivers/marvell/comphy/phy-comphy-3700.c +++ b/drivers/marvell/comphy/phy-comphy-3700.c @@ -402,7 +402,7 @@ static int mvebu_a3700_comphy_sgmii_power_on(uint8_t comphy_index, * 3. Set PHY input port PIN_PU_PLL=0, PIN_PU_RX=0, PIN_PU_TX=0. */ data = PIN_PU_IVREF_BIT | PIN_TX_IDLE_BIT | PIN_RESET_COMPHY_BIT; - mask = PIN_RESET_CORE_BIT | PIN_PU_PLL_BIT | PIN_PU_RX_BIT | + mask = data | PIN_RESET_CORE_BIT | PIN_PU_PLL_BIT | PIN_PU_RX_BIT | PIN_PU_TX_BIT; offset = MVEBU_COMPHY_REG_BASE + COMPHY_PHY_CFG1_OFFSET(comphy_index); reg_set(offset, data, mask); @@ -884,9 +884,9 @@ static int mvebu_a3700_comphy_pcie_power_on(uint8_t comphy_index, reg_set16(SYNC_PATTERN_REG_ADDR(PCIE) + COMPHY_SD_ADDR, data, mask); /* 11. Release SW reset */ - reg_set16(GLOB_PHY_CTRL0_ADDR(PCIE) + COMPHY_SD_ADDR, - MODE_CORE_CLK_FREQ_SEL | MODE_PIPE_WIDTH_32, - SOFT_RESET | MODE_REFDIV_MASK); + data = MODE_CORE_CLK_FREQ_SEL | MODE_PIPE_WIDTH_32; + mask = data | SOFT_RESET | MODE_REFDIV_MASK; + reg_set16(GLOB_PHY_CTRL0_ADDR(PCIE) + COMPHY_SD_ADDR, data, mask); /* Wait for > 55 us to allow PCLK be enabled */ udelay(PLL_SET_DELAY_US); |