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| author | Konstantin Porotchkin <kostap@marvell.com> | 2019-03-31 16:58:11 +0300 |
|---|---|---|
| committer | Marcin Wojtas <mw@semihalf.com> | 2020-06-19 18:03:29 +0200 |
| commit | 5a40d70f067b6238159142755e4e5cb27e292045 (patch) | |
| tree | 36471b2707cd04ade676b5a03df797c982cffa7c /drivers/marvell/cache_llc.c | |
| parent | 85440805d46646871dc9b2934a0a3932b44df7d4 (diff) | |
| download | arm-trusted-firmware-5a40d70f067b6238159142755e4e5cb27e292045.tar.gz | |
drivers: marvell: add support for mapping the entire LLC to SRAM
Add llc_sram_enable() and llc_sram_disable() APIs to Marvell
cache_lls driver.
Add LLC_SRAM definition to Marvell common makefile - disabled
by the default.
Add description of LLC_SRAM flag to the build documentation.
Change-Id: Ib348e09752ce1206d29268ef96c9018b781db182
Signed-off-by: Konstantin Porotchkin <kostap@marvell.com>
Diffstat (limited to 'drivers/marvell/cache_llc.c')
| -rw-r--r-- | drivers/marvell/cache_llc.c | 38 |
1 files changed, 38 insertions, 0 deletions
diff --git a/drivers/marvell/cache_llc.c b/drivers/marvell/cache_llc.c index 9b614c496..836aae7b8 100644 --- a/drivers/marvell/cache_llc.c +++ b/drivers/marvell/cache_llc.c @@ -109,3 +109,41 @@ void llc_runtime_enable(int ap_index) reg |= (0x1 << CCU_SET_POC_OFFSET); mmio_write_32(CCU_HTC_CR(ap_index), reg); } + +#if LLC_SRAM +void llc_sram_enable(int ap_index) +{ + uint32_t tc, way; + uint32_t way_addr; + + /* Lockdown all available ways for all traffic classes */ + for (tc = 0; tc < LLC_TC_NUM; tc++) + mmio_write_32(LLC_TCN_LOCK(ap_index, tc), LLC_WAY_MASK); + + /* Clear the high bits of SRAM address */ + mmio_write_32(LLC_BANKED_MNT_AHR(ap_index), 0); + + way_addr = PLAT_MARVELL_TRUSTED_RAM_BASE; + for (way = 0; way < LLC_WAYS; way++) { + /* Trigger allocation block command */ + mmio_write_32(LLC_BLK_ALOC(ap_index), + LLC_BLK_ALOC_BASE_ADDR(way_addr) | + LLC_BLK_ALOC_WAY_DATA_CLR | + LLC_BLK_ALOC_WAY_ID(way)); + way_addr += LLC_WAY_SIZE; + } + llc_enable(ap_index, 1); +} + +void llc_sram_disable(int ap_index) +{ + uint32_t tc; + + /* Disable the line lockings */ + for (tc = 0; tc < LLC_TC_NUM; tc++) + mmio_write_32(LLC_TCN_LOCK(ap_index, tc), 0); + + /* Invalidate all ways */ + llc_inv_all(ap_index); +} +#endif /* LLC_SRAM */ |