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| author | Bipin Ravi <bipin.ravi@arm.com> | 2023-03-14 11:03:24 -0500 |
|---|---|---|
| committer | Bipin Ravi <bipin.ravi@arm.com> | 2023-03-21 16:21:38 -0500 |
| commit | b01a59eb2a0456ca3ae6b8d020068ba846f813d4 (patch) | |
| tree | 15e2815f02bb2f4847bda4e041b3c83eae26fc3a /docs/design | |
| parent | 672eb21e26a41657b8146372d4283e794b430c5f (diff) | |
| download | arm-trusted-firmware-b01a59eb2a0456ca3ae6b8d020068ba846f813d4.tar.gz | |
fix(cpus): workaround for Cortex-A78C erratum 1827440
Cortex-A78C erratum 1827440 is a Cat B erratum that applies to
revision r0p0 and is fixed in r0p1.
The workaround is to set CPUACTLR2_EL1[2], which forces atomic store
operations to write-back memory to be performed in the L1 data cache.
SDEN documentation:
https://developer.arm.com/documentation/SDEN1707916/latest
Signed-off-by: Bipin Ravi <bipin.ravi@arm.com>
Change-Id: I41d8ef48f70216ec66bf2b0f4f03ea8d8c261ee7
Diffstat (limited to 'docs/design')
| -rw-r--r-- | docs/design/cpu-specific-build-macros.rst | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/docs/design/cpu-specific-build-macros.rst b/docs/design/cpu-specific-build-macros.rst index 73c7ac552..0f1f92aea 100644 --- a/docs/design/cpu-specific-build-macros.rst +++ b/docs/design/cpu-specific-build-macros.rst @@ -353,6 +353,10 @@ For Cortex-A78C, the following errata build flags are defined : Cortex-A78C CPU. This needs to be enabled for revision r0p0. The erratum is fixed in r0p1. +- ``ERRATA_A78C_1827440`` : This applies errata 1827440 workaround to + Cortex-A78C CPU. This needs to be enabled for revision r0p0. The erratum is + fixed in r0p1. + - ``ERRATA_A78C_2132064`` : This applies errata 2132064 workaround to Cortex-A78C CPU. This needs to be enabled for revisions r0p1, r0p2 and it is still open. |