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author | Boyan Karatotev <boyan.karatotev@arm.com> | 2022-10-03 14:21:28 +0100 |
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committer | Boyan Karatotev <boyan.karatotev@arm.com> | 2022-10-27 13:46:52 +0100 |
commit | 888eafa00b99aa06b4ff688407336811a7ff439a (patch) | |
tree | 55d2e351725568cb07a98dfb4f787190de836255 /docs/design | |
parent | 79544126943a90d31d81177655be11f75330ffed (diff) | |
download | arm-trusted-firmware-888eafa00b99aa06b4ff688407336811a7ff439a.tar.gz |
fix(cpus): workaround for Cortex-A710 erratum 2291219
Cortex-A710 erratum 2291219 is a Cat B erratum that applies to revisions
r0p0, r1p0, and r2p0, and is fixed in r2p1. The workaround is to set
CPUACTLR2_EL1[36] to 1 before the power down sequence that sets
CORE_PWRDN_EN. This allows the cpu to retry the power down and prevents
the deadlock. TF-A never clears this bit even if it wakes up from the
wfi in the sequence since it is not expected to do anything but retry to
power down after and the bit is cleared on reset.
SDEN can be found here:
https://developer.arm.com/documentation/SDEN1775101/latest
Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com>
Change-Id: I7d3a97dfac0c433c0be386c1f3d2f2e895a3f691
Diffstat (limited to 'docs/design')
-rw-r--r-- | docs/design/cpu-specific-build-macros.rst | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/docs/design/cpu-specific-build-macros.rst b/docs/design/cpu-specific-build-macros.rst index 91f712aaf..7ba79b9ad 100644 --- a/docs/design/cpu-specific-build-macros.rst +++ b/docs/design/cpu-specific-build-macros.rst @@ -495,6 +495,10 @@ For Cortex-A710, the following errata build flags are defined : Cortex-A710 CPU. This needs to be enabled for revisions r0p0, r1p0 and r2p0 of the CPU and is fixed in r2p1. +- ``ERRATA_A710_2291219``: This applies errata 2291219 workaround to + Cortex-A710 CPU. This needs to be enabled for revisions r0p0, r1p0 and r2p0 + of the CPU and is fixed in r2p1. + - ``ERRATA_A710_2008768``: This applies errata 2008768 workaround to Cortex-A710 CPU. This needs to be enabled for revisions r0p0, r1p0 and r2p0 of the CPU and is fixed in r2p1. |