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| author | Boyan Karatotev <boyan.karatotev@arm.com> | 2022-12-06 09:03:42 +0000 |
|---|---|---|
| committer | Boyan Karatotev <boyan.karatotev@arm.com> | 2023-05-05 13:16:18 +0100 |
| commit | 1d6d6802dd547c8b378a9a47572ee72e68cceb3b (patch) | |
| tree | 19fadcc58926f0b34dcff47a64d9f0893958f890 /bl1/aarch64/bl1_exceptions.S | |
| parent | 1d0d5e40206c693e24b0a4de7dbcfc4b79f3138e (diff) | |
| download | arm-trusted-firmware-1d6d6802dd547c8b378a9a47572ee72e68cceb3b.tar.gz | |
fix(pmu): unconditionally save PMCR_EL0
Reading back a RES0 bit does not necessarily mean it will be read as 0.
The Arm ARM explicitly warns against doing this. The PMU initialisation
code tries to set such bits to 1 (in MDCR_EL3) regardless of whether
they are in use or are RES0, checking their value could be wrong and
PMCR_EL0 might not end up being saved.
Save PMCR_EL0 unconditionally to prevent this. Remove the security state
change as the outgoing state is not relevant to what the root world
context should look like.
Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com>
Change-Id: Id43667d37b0e2da3ded0beaf23fa0d4f9013f470
Diffstat (limited to 'bl1/aarch64/bl1_exceptions.S')
| -rw-r--r-- | bl1/aarch64/bl1_exceptions.S | 4 |
1 files changed, 1 insertions, 3 deletions
diff --git a/bl1/aarch64/bl1_exceptions.S b/bl1/aarch64/bl1_exceptions.S index c54219fc1..eaaf59a22 100644 --- a/bl1/aarch64/bl1_exceptions.S +++ b/bl1/aarch64/bl1_exceptions.S @@ -218,9 +218,7 @@ unexpected_sync_exception: smc_handler: /* ----------------------------------------------------- * Save x0-x29 and ARMv8.3-PAuth (if enabled) registers. - * If Secure Cycle Counter is not disabled in MDCR_EL3 - * when ARMv8.5-PMU is implemented, save PMCR_EL0 and - * disable Cycle Counter. + * Save PMCR_EL0 and disable Cycle Counter. * TODO: Revisit to store only SMCCC specified registers. * ----------------------------------------------------- */ |