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author | Krishna Sitaraman <ksitaraman@nvidia.com> | 2016-07-28 13:56:36 -0700 |
---|---|---|
committer | Varun Wadekar <vwadekar@nvidia.com> | 2017-04-05 14:09:51 -0700 |
commit | ac26b96b40c4cda751f1923b4906d7027e529327 (patch) | |
tree | 3d8e5c1df80d3f1e7e4693def0ac45a248bb30e2 | |
parent | 25621454d53a18bd516c7f35b94266fa7aeca7bb (diff) | |
download | arm-trusted-firmware-ac26b96b40c4cda751f1923b4906d7027e529327.tar.gz |
Tegra186: update t18x_ari.h to v3.0
This patch updates the ARI header to version 3.0
Change-Id: I7cfe0c61c80a6b78625232135dd63393602d32fe
Signed-off-by: Krishna Sitaraman <ksitaraman@nvidia.com>
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
-rw-r--r-- | plat/nvidia/tegra/soc/t186/drivers/include/t18x_ari.h | 62 |
1 files changed, 31 insertions, 31 deletions
diff --git a/plat/nvidia/tegra/soc/t186/drivers/include/t18x_ari.h b/plat/nvidia/tegra/soc/t186/drivers/include/t18x_ari.h index 3e6054bd0..cb48de62f 100644 --- a/plat/nvidia/tegra/soc/t186/drivers/include/t18x_ari.h +++ b/plat/nvidia/tegra/soc/t186/drivers/include/t18x_ari.h @@ -40,8 +40,8 @@ */ enum { - TEGRA_ARI_VERSION_MAJOR = 2, - TEGRA_ARI_VERSION_MINOR = 19, + TEGRA_ARI_VERSION_MAJOR = 3, + TEGRA_ARI_VERSION_MINOR = 0, }; typedef enum { @@ -107,15 +107,15 @@ typedef enum { typedef enum { TEGRA_ARI_CCPLEX_CCP0 = 0, TEGRA_ARI_CCPLEX_CCP1 = 1, - TEGRA_ARI_CCPLEX_CCP3 = 3, + TEGRA_ARI_CCPLEX_CCP3 = 3, /* obsoleted */ } tegra_ari_ccplex_sleep_state_t; typedef enum { TEGRA_ARI_SYSTEM_SC0 = 0, - TEGRA_ARI_SYSTEM_SC1 = 1, - TEGRA_ARI_SYSTEM_SC2 = 2, - TEGRA_ARI_SYSTEM_SC3 = 3, - TEGRA_ARI_SYSTEM_SC4 = 4, + TEGRA_ARI_SYSTEM_SC1 = 1, /* obsoleted */ + TEGRA_ARI_SYSTEM_SC2 = 2, /* obsoleted */ + TEGRA_ARI_SYSTEM_SC3 = 3, /* obsoleted */ + TEGRA_ARI_SYSTEM_SC4 = 4, /* obsoleted */ TEGRA_ARI_SYSTEM_SC7 = 7, TEGRA_ARI_SYSTEM_SC8 = 8, } tegra_ari_system_sleep_state_t; @@ -124,21 +124,22 @@ typedef enum { TEGRA_ARI_CROSSOVER_C1_C6 = 0, TEGRA_ARI_CROSSOVER_CC1_CC6 = 1, TEGRA_ARI_CROSSOVER_CC1_CC7 = 2, - TEGRA_ARI_CROSSOVER_CCP1_CCP3 = 3, - TEGRA_ARI_CROSSOVER_CCP3_SC2 = 4, - TEGRA_ARI_CROSSOVER_CCP3_SC3 = 5, - TEGRA_ARI_CROSSOVER_CCP3_SC4 = 6, - TEGRA_ARI_CROSSOVER_CCP3_SC7 = 7, - TEGRA_ARI_CROSSOVER_CCP3_SC1 = 8, + TEGRA_ARI_CROSSOVER_CCP1_CCP3 = 3, /* obsoleted */ + TEGRA_ARI_CROSSOVER_CCP3_SC2 = 4, /* obsoleted */ + TEGRA_ARI_CROSSOVER_CCP3_SC3 = 5, /* obsoleted */ + TEGRA_ARI_CROSSOVER_CCP3_SC4 = 6, /* obsoleted */ + TEGRA_ARI_CROSSOVER_CCP3_SC7 = 7, /* obsoleted */ + TEGRA_ARI_CROSSOVER_SC0_SC7 = 7, + TEGRA_ARI_CROSSOVER_CCP3_SC1 = 8, /* obsoleted */ } tegra_ari_crossover_index_t; typedef enum { TEGRA_ARI_CSTATE_STATS_CLEAR = 0, - TEGRA_ARI_CSTATE_STATS_SC7_ENTRIES = 1, - TEGRA_ARI_CSTATE_STATS_SC4_ENTRIES, - TEGRA_ARI_CSTATE_STATS_SC3_ENTRIES, - TEGRA_ARI_CSTATE_STATS_SC2_ENTRIES, - TEGRA_ARI_CSTATE_STATS_CCP3_ENTRIES, + TEGRA_ARI_CSTATE_STATS_SC7_ENTRIES, + TEGRA_ARI_CSTATE_STATS_SC4_ENTRIES, /* obsoleted */ + TEGRA_ARI_CSTATE_STATS_SC3_ENTRIES, /* obsoleted */ + TEGRA_ARI_CSTATE_STATS_SC2_ENTRIES, /* obsoleted */ + TEGRA_ARI_CSTATE_STATS_CCP3_ENTRIES, /* obsoleted */ TEGRA_ARI_CSTATE_STATS_A57_CC6_ENTRIES, TEGRA_ARI_CSTATE_STATS_A57_CC7_ENTRIES, TEGRA_ARI_CSTATE_STATS_D15_CC6_ENTRIES, @@ -403,17 +404,18 @@ typedef enum { TEGRA_NVG_CHANNEL_CROSSOVER_C1_C6 = 5, TEGRA_NVG_CHANNEL_CROSSOVER_CC1_CC6 = 6, TEGRA_NVG_CHANNEL_CROSSOVER_CC1_CC7 = 7, - TEGRA_NVG_CHANNEL_CROSSOVER_CCP1_CCP3 = 8, - TEGRA_NVG_CHANNEL_CROSSOVER_CCP3_SC2 = 9, - TEGRA_NVG_CHANNEL_CROSSOVER_CCP3_SC3 = 10, - TEGRA_NVG_CHANNEL_CROSSOVER_CCP3_SC4 = 11, - TEGRA_NVG_CHANNEL_CROSSOVER_CCP3_SC7 = 12, + TEGRA_NVG_CHANNEL_CROSSOVER_CCP1_CCP3 = 8, /* obsoleted */ + TEGRA_NVG_CHANNEL_CROSSOVER_CCP3_SC2 = 9, /* obsoleted */ + TEGRA_NVG_CHANNEL_CROSSOVER_CCP3_SC3 = 10, /* obsoleted */ + TEGRA_NVG_CHANNEL_CROSSOVER_CCP3_SC4 = 11, /* obsoleted */ + TEGRA_NVG_CHANNEL_CROSSOVER_CCP3_SC7 = 12, /* obsoleted */ + TEGRA_NVG_CHANNEL_CROSSOVER_SC0_SC7 = 12, TEGRA_NVG_CHANNEL_CSTATE_STATS_CLEAR = 13, TEGRA_NVG_CHANNEL_CSTATE_STATS_SC7_ENTRIES = 14, - TEGRA_NVG_CHANNEL_CSTATE_STATS_SC4_ENTRIES = 15, - TEGRA_NVG_CHANNEL_CSTATE_STATS_SC3_ENTRIES = 16, - TEGRA_NVG_CHANNEL_CSTATE_STATS_SC2_ENTRIES = 17, - TEGRA_NVG_CHANNEL_CSTATE_STATS_CCP3_ENTRIES = 18, + TEGRA_NVG_CHANNEL_CSTATE_STATS_SC4_ENTRIES = 15, /* obsoleted */ + TEGRA_NVG_CHANNEL_CSTATE_STATS_SC3_ENTRIES = 16, /* obsoleted */ + TEGRA_NVG_CHANNEL_CSTATE_STATS_SC2_ENTRIES = 17, /* obsoleted */ + TEGRA_NVG_CHANNEL_CSTATE_STATS_CCP3_ENTRIES = 18, /* obsoleted */ TEGRA_NVG_CHANNEL_CSTATE_STATS_A57_CC6_ENTRIES = 19, TEGRA_NVG_CHANNEL_CSTATE_STATS_A57_CC7_ENTRIES = 20, TEGRA_NVG_CHANNEL_CSTATE_STATS_D15_CC6_ENTRIES = 21, @@ -432,7 +434,7 @@ typedef enum { TEGRA_NVG_CHANNEL_CSTATE_STATS_A57_3_C7_ENTRIES = 34, TEGRA_NVG_CHANNEL_CSTATE_STATS_LAST_CSTATE_ENTRY_D15_0 = 35, TEGRA_NVG_CHANNEL_CSTATE_STATS_LAST_CSTATE_ENTRY_D15_1 = 36, - TEGRA_NVG_CHANNEL_CSTATE_STATS_LAST_CSTATE_ENTRY_D15_2 = 37, /* Reserved (for Denver15 core 2) */ + TEGRA_NVG_CHANNEL_CSTATE_STATS_LAST_CSTATE_ENTRY_D15_2 = 37, /* Reserved (for Denver15 core 2) */ TEGRA_NVG_CHANNEL_CSTATE_STATS_LAST_CSTATE_ENTRY_D15_3 = 38, /* Reserved (for Denver15 core 3) */ TEGRA_NVG_CHANNEL_CSTATE_STATS_LAST_CSTATE_ENTRY_A57_0 = 39, TEGRA_NVG_CHANNEL_CSTATE_STATS_LAST_CSTATE_ENTRY_A57_1 = 40, @@ -441,10 +443,8 @@ typedef enum { TEGRA_NVG_CHANNEL_IS_SC7_ALLOWED = 43, TEGRA_NVG_CHANNEL_ONLINE_CORE = 44, TEGRA_NVG_CHANNEL_CC3_CTRL = 45, - TEGRA_NVG_CHANNEL_CROSSOVER_CCP3_SC1 = 46, + TEGRA_NVG_CHANNEL_CROSSOVER_CCP3_SC1 = 46, /* obsoleted */ TEGRA_NVG_CHANNEL_LAST_INDEX, } tegra_nvg_channel_id_t; #endif /* T18X_TEGRA_ARI_H */ - - |