[PowerPC] Add vec_vsx_ld and vec_vsx_st intrinsics

This patch enables the vec_vsx_ld and vec_vsx_st intrinsics for
PowerPC, which provide programmer access to the lxvd2x, lxvw4x,
stxvd2x, and stxvw4x instructions.

New code in altivec.h defines these in terms of new builtins, which
are themselves defined in BuiltinsPPC.def.  The builtins are converted
to LLVM intrinsics in CGBuiltin.cpp.  Additional code is added to
builtins-ppc-vsx.c to verify the correct generation of the intrinsics.

Note that I moved the other VSX builtins so all VSX builtins will be
alphabetical in their own section in BuiltinsPPC.def.

There is a companion patch for LLVM.


git-svn-id: https://llvm.org/svn/llvm-project/cfe/trunk@221768 91177308-0d34-0410-b5e6-96231b3b80d8

1 files changed, 48 insertions, 0 deletions

diff --git a/test/CodeGen/builtins-ppc-vsx.c b/test/CodeGen/builtins-ppc-vsx.c
index bae961456e..9bd0a5df6f 100644
--- a/test/CodeGen/builtins-ppc-vsx.c
+++ b/test/CodeGen/builtins-ppc-vsx.c
@@ -3,10 +3,18 @@
 
 vector float vf = { -1.5, 2.5, -3.5, 4.5 };
 vector double vd = { 3.5, -7.5 };
+vector signed int vsi = { -1, 2, -3, 4 };
+vector unsigned int vui = { 0, 1, 2, 3 };
+vector signed long long vsll = { 255LL, -937LL };
+vector unsigned long long vull = { 1447LL, 2894LL };
 double d = 23.4;
 
 vector float res_vf;
 vector double res_vd;
+vector signed int res_vsi;
+vector unsigned int res_vui;
+vector signed long long res_vsll;
+vector unsigned long long res_vull;
 double res_d;
 
 void test1() {
@@ -37,4 +45,44 @@ void test1() {
 
   res_d = __builtin_vsx_xsmindp(d, d);
 // CHECK: @llvm.ppc.vsx.xsmindp
+
+  /* vec_vsx_ld */
+
+  res_vsi = vec_vsx_ld(0, &vsi);
+// CHECK: @llvm.ppc.vsx.lxvw4x
+
+  res_vui = vec_vsx_ld(0, &vui);
+// CHECK: @llvm.ppc.vsx.lxvw4x
+
+  res_vf = vec_vsx_ld (0, &vf);
+// CHECK: @llvm.ppc.vsx.lxvw4x
+
+  res_vsll = vec_vsx_ld(0, &vsll);
+// CHECK: @llvm.ppc.vsx.lxvd2x
+
+  res_vull = vec_vsx_ld(0, &vull);
+// CHECK: @llvm.ppc.vsx.lxvd2x
+
+  res_vd = vec_vsx_ld(0, &vd);
+// CHECK: @llvm.ppc.vsx.lxvd2x
+
+  /* vec_vsx_st */
+
+  vec_vsx_st(vsi, 0, &res_vsi);
+// CHECK: @llvm.ppc.vsx.stxvw4x
+
+  vec_vsx_st(vui, 0, &res_vui);
+// CHECK: @llvm.ppc.vsx.stxvw4x
+
+  vec_vsx_st(vf, 0, &res_vf);
+// CHECK: @llvm.ppc.vsx.stxvw4x
+
+  vec_vsx_st(vsll, 0, &res_vsll);
+// CHECK: @llvm.ppc.vsx.stxvd2x
+
+  vec_vsx_st(vull, 0, &res_vull);
+// CHECK: @llvm.ppc.vsx.stxvd2x
+
+  vec_vsx_st(vd, 0, &res_vd);
+// CHECK: @llvm.ppc.vsx.stxvd2x
 }