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| author | Craig Topper <craig.topper@gmail.com> | 2015-11-11 08:00:41 +0000 |
|---|---|---|
| committer | Craig Topper <craig.topper@gmail.com> | 2015-11-11 08:00:41 +0000 |
| commit | 271fd30fa4b44d153568a573b1b447307fd1bce4 (patch) | |
| tree | 4fb11016cddb164a02d868150e392cf9507175c3 /test/CodeGen/sse-builtins.c | |
| parent | 9477983ae410dacaf671729803953c63faa5e95f (diff) | |
| download | clang-271fd30fa4b44d153568a573b1b447307fd1bce4.tar.gz | |
[X86] Use __builtin_ia32_paddq and __builtin_ia32_psubq to implement a couple intrinsics that were supposed to operate on MMX registers. Otherwise we end up operating on GPRs. Throw in a test for _mm_mul_su32 while I was there.
git-svn-id: https://llvm.org/svn/llvm-project/cfe/trunk@252711 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'test/CodeGen/sse-builtins.c')
| -rw-r--r-- | test/CodeGen/sse-builtins.c | 18 |
1 files changed, 18 insertions, 0 deletions
diff --git a/test/CodeGen/sse-builtins.c b/test/CodeGen/sse-builtins.c index 11a094aad7..fce57b665f 100644 --- a/test/CodeGen/sse-builtins.c +++ b/test/CodeGen/sse-builtins.c @@ -495,3 +495,21 @@ __m128i test_mm_undefined_si128() { // CHECK: ret <2 x i64> undef return _mm_undefined_si128(); } + +__m64 test_mm_add_si64(__m64 __a, __m64 __b) { + // CHECK-LABEL: @test_mm_add_si64 + // CHECK @llvm.x86.mmx.padd.q(x86_mmx %{{.*}}, x86_mmx %{{.*}}) + return _mm_add_si64(__a, __b); +} + +__m64 test_mm_sub_si64(__m64 __a, __m64 __b) { + // CHECK-LABEL: @test_mm_sub_si64 + // CHECK @llvm.x86.mmx.psub.q(x86_mmx %{{.*}}, x86_mmx %{{.*}}) + return _mm_sub_si64(__a, __b); +} + +__m64 test_mm_mul_su32(__m64 __a, __m64 __b) { + // CHECK-LABEL: @test_mm_mul_su32 + // CHECK @llvm.x86.mmx.pmulu.dq(x86_mmx %{{.*}}, x86_mmx %{{.*}}) + return _mm_mul_su32(__a, __b); +} |