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| author | Justin Holewinski <jholewinski@nvidia.com> | 2013-06-21 22:39:56 +0000 |
|---|---|---|
| committer | Justin Holewinski <jholewinski@nvidia.com> | 2013-06-21 22:39:56 +0000 |
| commit | adebeb8bdc4ae7a841ee65d45d406dcba6e74e25 (patch) | |
| tree | 2d0f20e131fb6cb873c6d8deb3f1eaa132a60c1d /test/CodeGen/nvptx-inlineasm-ptx.c | |
| parent | e9ccbeedd2a5198c6e11077299354fde464284a8 (diff) | |
| download | clang-adebeb8bdc4ae7a841ee65d45d406dcba6e74e25.tar.gz | |
[NVPTX] Fix inline asm test case to use LLVM IR instead of PTX so it works even when the NVPTX target is not built
git-svn-id: https://llvm.org/svn/llvm-project/cfe/trunk@184601 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'test/CodeGen/nvptx-inlineasm-ptx.c')
| -rw-r--r-- | test/CodeGen/nvptx-inlineasm-ptx.c | 24 |
1 files changed, 12 insertions, 12 deletions
diff --git a/test/CodeGen/nvptx-inlineasm-ptx.c b/test/CodeGen/nvptx-inlineasm-ptx.c index 8432e6c271..0a19123ee0 100644 --- a/test/CodeGen/nvptx-inlineasm-ptx.c +++ b/test/CodeGen/nvptx-inlineasm-ptx.c @@ -1,5 +1,5 @@ -// RUN: %clang_cc1 -triple nvptx-unknown-unknown -O3 -S -o - %s | FileCheck %s -// RUN: %clang_cc1 -triple nvptx64-unknown-unknown -O3 -S -o - %s | FileCheck %s +// RUN: %clang_cc1 -triple nvptx-unknown-unknown -O3 -S -o - %s -emit-llvm | FileCheck %s +// RUN: %clang_cc1 -triple nvptx64-unknown-unknown -O3 -S -o - %s -emit-llvm | FileCheck %s void constraints() { char c; @@ -13,28 +13,28 @@ void constraints() { float f; double d; - // CHECK: mov.b8 %rc{{[0-9]+}}, %rc{{[0-9]+}} + // CHECK: i8 asm sideeffect "mov.b8 $0, $1;", "=c,c" asm volatile ("mov.b8 %0, %1;" : "=c"(c) : "c"(c)); - // CHECK: mov.b8 %rc{{[0-9]+}}, %rc{{[0-9]+}} + // CHECK: i8 asm sideeffect "mov.b8 $0, $1;", "=c,c" asm volatile ("mov.b8 %0, %1;" : "=c"(uc) : "c"(uc)); - // CHECK: mov.b16 %rs{{[0-9]+}}, %rs{{[0-9]+}} + // CHECK: i16 asm sideeffect "mov.b16 $0, $1;", "=h,h" asm volatile ("mov.b16 %0, %1;" : "=h"(s) : "h"(s)); - // CHECK: mov.b16 %rs{{[0-9]+}}, %rs{{[0-9]+}} + // CHECK: i16 asm sideeffect "mov.b16 $0, $1;", "=h,h" asm volatile ("mov.b16 %0, %1;" : "=h"(us) : "h"(us)); - // CHECK: mov.b32 %r{{[0-9]+}}, %r{{[0-9]+}} + // CHECK: i32 asm sideeffect "mov.b32 $0, $1;", "=r,r" asm volatile ("mov.b32 %0, %1;" : "=r"(i) : "r"(i)); - // CHECK: mov.b32 %r{{[0-9]+}}, %r{{[0-9]+}} + // CHECK: i32 asm sideeffect "mov.b32 $0, $1;", "=r,r" asm volatile ("mov.b32 %0, %1;" : "=r"(ui) : "r"(ui)); - // CHECK: mov.b64 %rl{{[0-9]+}}, %rl{{[0-9]+}} + // CHECK: i64 asm sideeffect "mov.b64 $0, $1;", "=l,l" asm volatile ("mov.b64 %0, %1;" : "=l"(l) : "l"(l)); - // CHECK: mov.b64 %rl{{[0-9]+}}, %rl{{[0-9]+}} + // CHECK: i64 asm sideeffect "mov.b64 $0, $1;", "=l,l" asm volatile ("mov.b64 %0, %1;" : "=l"(ul) : "l"(ul)); - // CHECK: mov.b32 %f{{[0-9]+}}, %f{{[0-9]+}} + // CHECK: float asm sideeffect "mov.b32 $0, $1;", "=f,f" asm volatile ("mov.b32 %0, %1;" : "=f"(f) : "f"(f)); - // CHECK: mov.b64 %fl{{[0-9]+}}, %fl{{[0-9]+}} + // CHECK: double asm sideeffect "mov.b64 $0, $1;", "=d,d" asm volatile ("mov.b64 %0, %1;" : "=d"(d) : "d"(d)); } |