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authorReid Kleckner <rnk@google.com>2017-05-04 18:19:52 +0000
committerReid Kleckner <rnk@google.com>2017-05-04 18:19:52 +0000
commit1895863dfb107f56cfedc3059f5489787d043290 (patch)
treed851dc6bdefa6bef32e09a60ef3437a621ad6e54 /test/CodeGen/ms-inline-asm-avx512.c
parente8c1a7cf0fca45bbc04a7c26c5d0fcd47a3aeac0 (diff)
downloadclang-1895863dfb107f56cfedc3059f5489787d043290.tar.gz
[ms-inline-asm] Use the frontend size only for ambiguous instructions
This avoids problems on code like this: char buf[16]; __asm { movups xmm0, [buf] mov [buf], eax } The frontend size in this case (1) is wrong, and the register makes the instruction matching unambiguous. There are also enough bytes available that we shouldn't complain to the user that they are potentially using an incorrectly sized instruction to access the variable. Supersedes D32636 and D26586 and fixes PR28266 git-svn-id: https://llvm.org/svn/llvm-project/cfe/trunk@302179 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'test/CodeGen/ms-inline-asm-avx512.c')
-rw-r--r--test/CodeGen/ms-inline-asm-avx512.c15
1 files changed, 14 insertions, 1 deletions
diff --git a/test/CodeGen/ms-inline-asm-avx512.c b/test/CodeGen/ms-inline-asm-avx512.c
index c1b783a210..6189e50d21 100644
--- a/test/CodeGen/ms-inline-asm-avx512.c
+++ b/test/CodeGen/ms-inline-asm-avx512.c
@@ -1,5 +1,5 @@
// REQUIRES: x86-registered-target
-// RUN: %clang_cc1 %s -triple x86_64-pc-windows-msvc -target-cpu knl -fasm-blocks -emit-llvm -o - | FileCheck %s
+// RUN: %clang_cc1 %s -triple x86_64-pc-windows-msvc -target-cpu skylake-avx512 -fasm-blocks -emit-llvm -o - | FileCheck %s
void t1() {
// CHECK: @t1
@@ -19,3 +19,16 @@ void t2() {
vaddpd zmm8 {k1}, zmm27, zmm6
}
}
+
+void ignore_fe_size() {
+ // CHECK-LABEL: define void @ignore_fe_size()
+ char c;
+ // CHECK: vaddps xmm1, xmm2, $1{1to4}
+ __asm vaddps xmm1, xmm2, [c]{1to4}
+ // CHECK: vaddps xmm1, xmm2, $2
+ __asm vaddps xmm1, xmm2, [c]
+ // CHECK: mov eax, $3
+ __asm mov eax, [c]
+ // CHECK: mov $0, rax
+ __asm mov [c], rax
+}