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| author | Tim Northover <tnorthover@apple.com> | 2014-03-29 15:09:45 +0000 |
|---|---|---|
| committer | Tim Northover <tnorthover@apple.com> | 2014-03-29 15:09:45 +0000 |
| commit | 7e0e8ef787107d4f646254130625d83c67a617bf (patch) | |
| tree | 8ff59170f29defadd4d7bea0156c174fd1619a4d /test/CodeGen/arm64_vdup.c | |
| parent | 6614bf2dd1f7e09bbef38b243fd42f7182897908 (diff) | |
| download | clang-7e0e8ef787107d4f646254130625d83c67a617bf.tar.gz | |
ARM64: initial clang support commit.
This adds Clang support for the ARM64 backend. There are definitely
still some rough edges, so please bring up any issues you see with
this patch.
As with the LLVM commit though, we think it'll be more useful for
merging with AArch64 from within the tree.
git-svn-id: https://llvm.org/svn/llvm-project/cfe/trunk@205100 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'test/CodeGen/arm64_vdup.c')
| -rw-r--r-- | test/CodeGen/arm64_vdup.c | 42 |
1 files changed, 42 insertions, 0 deletions
diff --git a/test/CodeGen/arm64_vdup.c b/test/CodeGen/arm64_vdup.c new file mode 100644 index 0000000000..f9773e4f47 --- /dev/null +++ b/test/CodeGen/arm64_vdup.c @@ -0,0 +1,42 @@ +// RUN: %clang -target arm64-apple-ios7 -ffreestanding -S -o - -emit-llvm %s | FileCheck %s +// Test ARM64 SIMD duplicate lane and n intrinsics + +#include <arm_neon.h> + +void test_vdup_lane_s64(int64x1_t a1) { + // CHECK-LABEL: test_vdup_lane_s64 + vdup_lane_s64(a1, 0); + // CHECK: shufflevector +} + +void test_vdup_lane_u64(uint64x1_t a1) { + // CHECK-LABEL: test_vdup_lane_u64 + vdup_lane_u64(a1, 0); + // CHECK: shufflevector +} + +// uncomment out the following code once scalar_to_vector in the backend +// works (for 64 bit?). Change the "CHECK@" to "CHECK<colon>" +/* +float64x1_t test_vdup_n_f64(float64_t a1) { + // CHECK-LABEL@ test_vdup_n_f64 + return vdup_n_f64(a1); + // match that an element is inserted into part 0 + // CHECK@ insertelement {{.*, i32 0 *$}} +} +*/ + +float16x8_t test_vdupq_n_f16(float16_t *a1) { + // CHECK-LABEL: test_vdupq_n_f16 + return vdupq_n_f16(*a1); + // match that an element is inserted into parts 0-7. The backend better + // turn that into a single dup intruction + // CHECK: insertelement {{.*, i32 0 *$}} + // CHECK: insertelement {{.*, i32 1 *$}} + // CHECK: insertelement {{.*, i32 2 *$}} + // CHECK: insertelement {{.*, i32 3 *$}} + // CHECK: insertelement {{.*, i32 4 *$}} + // CHECK: insertelement {{.*, i32 5 *$}} + // CHECK: insertelement {{.*, i32 6 *$}} + // CHECK: insertelement {{.*, i32 7 *$}} +} |