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| author | Peter Smith <peter.smith@linaro.org> | 2018-05-17 13:17:33 +0000 |
|---|---|---|
| committer | Peter Smith <peter.smith@linaro.org> | 2018-05-17 13:17:33 +0000 |
| commit | 33b2c38bcd8906312e586f0206d431be2d280025 (patch) | |
| tree | bd4fac304e73ad5d474ec9ae49a75f4be8526a40 /test/CodeGen/aarch64-inline-asm.c | |
| parent | ae156fd3e49c0a4cba72dc90a31b463c3f763e17 (diff) | |
| download | clang-33b2c38bcd8906312e586f0206d431be2d280025.tar.gz | |
[AArch64] Correct inline assembly test case for S modifier [NFC]
The existing test for the AArch64 inline assembly constraint S uses the
A and L modifiers. These modifiers were implemented in the original
AArch64 backend but were not carried forward to the merged backend. The
A is associated with ADRP and does nothing, the L is associated with
:lo12: . Given that A and L are not supported by GCC and not supported
by the new implementation of constraint S in LLVM (see D46745) I've
altered the test to put :lo12: directly in the string so that A and L
are not needed.
Differential Revision: https://reviews.llvm.org/D46932
git-svn-id: https://llvm.org/svn/llvm-project/cfe/trunk@332606 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'test/CodeGen/aarch64-inline-asm.c')
| -rw-r--r-- | test/CodeGen/aarch64-inline-asm.c | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/test/CodeGen/aarch64-inline-asm.c b/test/CodeGen/aarch64-inline-asm.c index 264df9d5fc..0889a7157f 100644 --- a/test/CodeGen/aarch64-inline-asm.c +++ b/test/CodeGen/aarch64-inline-asm.c @@ -44,9 +44,9 @@ void test_constraints_immed(void) { void test_constraint_S(void) { int *addr; - asm("adrp %0, %A1\n\t" - "add %0, %0, %L1" : "=r"(addr) : "S"(&var)); -// CHECK: call i32* asm "adrp $0, ${1:A}\0A\09add $0, $0, ${1:L}", "=r,S"(i64* @var) + asm("adrp %0, %1\n\t" + "add %0, %0, :lo12:%1" : "=r"(addr) : "S"(&var)); +// CHECK: call i32* asm "adrp $0, $1\0A\09add $0, $0, :lo12:$1", "=r,S"(i64* @var) } void test_constraint_Q(void) { |