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| author | Craig Topper <craig.topper@intel.com> | 2019-09-11 23:54:36 +0000 |
|---|---|---|
| committer | Craig Topper <craig.topper@intel.com> | 2019-09-11 23:54:36 +0000 |
| commit | f38445a332418eb3fa4a707d3a6d40e11a6c3601 (patch) | |
| tree | 6e28d3e33f6fc17be60a8228bf2ff80c058faa40 /docs | |
| parent | 2dc92c44938e1fedf3c43f0151ec408b93da6a65 (diff) | |
| download | clang-f38445a332418eb3fa4a707d3a6d40e11a6c3601.tar.gz | |
[X86] Enable -mprefer-vector-width=256 by default for Skylake-avx512 and later Intel CPUs.
AVX512 instructions can cause a frequency drop on these CPUs. This
can negate the performance gains from using wider vectors. Enabling
prefer-vector-width=256 will prevent generation of zmm registers
unless explicit 512 bit operations are used in the original source
code.
I believe gcc and icc both do something similar to this by default.
Differential Revision: https://reviews.llvm.org/D67259
git-svn-id: https://llvm.org/svn/llvm-project/cfe/trunk@371694 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'docs')
| -rw-r--r-- | docs/ReleaseNotes.rst | 8 |
1 files changed, 6 insertions, 2 deletions
diff --git a/docs/ReleaseNotes.rst b/docs/ReleaseNotes.rst index e764bbb7f0..9716360a78 100644 --- a/docs/ReleaseNotes.rst +++ b/docs/ReleaseNotes.rst @@ -56,8 +56,12 @@ Improvements to Clang's diagnostics Non-comprehensive list of changes in this release ------------------------------------------------- -- ... - +- For X86 target, -march=skylake-avx512, -march=icelake-client, + -march=icelake-server, -march=cascadelake, -march=cooperlake will default to + not using 512-bit zmm registers in vectorized code unless 512-bit intrinsics + are used in the source code. 512-bit operations are known to cause the CPUs + to run at a lower frequency which can impact performance. This behavior can be + changed by passing -mprefer-vector-width=512 on the command line. New Compiler Flags ------------------ |