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-rw-r--r--bfd/ChangeLog11
-rw-r--r--bfd/archures.c1
-rw-r--r--bfd/bfd-in2.h1
-rw-r--r--bfd/cpu-mips.c2
-rw-r--r--bfd/elfxx-mips.c8
-rw-r--r--gas/ChangeLog7
-rw-r--r--gas/config/tc-mips.c3
-rw-r--r--gas/doc/c-mips.texi1
-rw-r--r--gas/testsuite/ChangeLog8
-rw-r--r--gas/testsuite/gas/mips/mips.exp4
-rw-r--r--gas/testsuite/gas/mips/octeon2.d38
-rw-r--r--gas/testsuite/gas/mips/octeon2.s38
-rw-r--r--include/opcode/ChangeLog8
-rw-r--r--include/opcode/mips.h6
-rw-r--r--opcodes/ChangeLog17
-rw-r--r--opcodes/mips-dis.c6
-rw-r--r--opcodes/mips-opc.c39
17 files changed, 189 insertions, 9 deletions
diff --git a/bfd/ChangeLog b/bfd/ChangeLog
index 6b1e88a487..6b9491fd21 100644
--- a/bfd/ChangeLog
+++ b/bfd/ChangeLog
@@ -1,3 +1,14 @@
+2011-12-08 Andrew Pinski <apinski@cavium.com>
+ Adam Nemet <anemet@caviumnetworks.com>
+
+ * archures.c (bfd_mach_mips_octeon2): New macro
+ * bfd-in2.h: Regenerate.
+ * cpu-mips.c (I_mipsocteon2): New enum value.
+ (arch_info_struct): Add bfd_mach_mips_octeon2.
+ * elfxx-mips.c (_bfd_elf_mips_mach): Support E_MIPS_MACH_OCTEON2.
+ (mips_set_isa_flags): Add bfd_mach_mips_octeon2.
+ (mips_mach_extensions): Add bfd_mach_mips_octeon2.
+
2011-12-07 Alan Modra <amodra@gmail.com>
PR ld/12772
diff --git a/bfd/archures.c b/bfd/archures.c
index 698155fbc6..f609534900 100644
--- a/bfd/archures.c
+++ b/bfd/archures.c
@@ -177,6 +177,7 @@ DESCRIPTION
.#define bfd_mach_mips_sb1 12310201 {* octal 'SB', 01 *}
.#define bfd_mach_mips_octeon 6501
.#define bfd_mach_mips_octeonp 6601
+.#define bfd_mach_mips_octeon2 6502
.#define bfd_mach_mips_xlr 887682 {* decimal 'XLR' *}
.#define bfd_mach_mipsisa32 32
.#define bfd_mach_mipsisa32r2 33
diff --git a/bfd/bfd-in2.h b/bfd/bfd-in2.h
index 14e0d1a1f6..2bb0ec7db5 100644
--- a/bfd/bfd-in2.h
+++ b/bfd/bfd-in2.h
@@ -1883,6 +1883,7 @@ enum bfd_architecture
#define bfd_mach_mips_sb1 12310201 /* octal 'SB', 01 */
#define bfd_mach_mips_octeon 6501
#define bfd_mach_mips_octeonp 6601
+#define bfd_mach_mips_octeon2 6502
#define bfd_mach_mips_xlr 887682 /* decimal 'XLR' */
#define bfd_mach_mipsisa32 32
#define bfd_mach_mipsisa32r2 33
diff --git a/bfd/cpu-mips.c b/bfd/cpu-mips.c
index 417bc7cf4c..ed86f11fb8 100644
--- a/bfd/cpu-mips.c
+++ b/bfd/cpu-mips.c
@@ -94,6 +94,7 @@ enum
I_loongson_3a,
I_mipsocteon,
I_mipsocteonp,
+ I_mipsocteon2,
I_xlr,
I_micromips
};
@@ -136,6 +137,7 @@ static const bfd_arch_info_type arch_info_struct[] =
N (64, 64, bfd_mach_mips_loongson_3a, "mips:loongson_3a", FALSE, NN(I_loongson_3a)),
N (64, 64, bfd_mach_mips_octeon,"mips:octeon", FALSE, NN(I_mipsocteon)),
N (64, 64, bfd_mach_mips_octeonp,"mips:octeon+", FALSE, NN(I_mipsocteonp)),
+ N (64, 64, bfd_mach_mips_octeon2,"mips:octeon2", FALSE, NN(I_mipsocteon2)),
N (64, 64, bfd_mach_mips_xlr, "mips:xlr", FALSE, NN(I_xlr)),
N (64, 64, bfd_mach_mips_micromips,"mips:micromips",FALSE,0)
};
diff --git a/bfd/elfxx-mips.c b/bfd/elfxx-mips.c
index 7a467c71bc..33b2e37c94 100644
--- a/bfd/elfxx-mips.c
+++ b/bfd/elfxx-mips.c
@@ -6182,6 +6182,9 @@ _bfd_elf_mips_mach (flagword flags)
case E_MIPS_MACH_LS3A:
return bfd_mach_mips_loongson_3a;
+ case E_MIPS_MACH_OCTEON2:
+ return bfd_mach_mips_octeon2;
+
case E_MIPS_MACH_OCTEON:
return bfd_mach_mips_octeon;
@@ -10893,6 +10896,10 @@ mips_set_isa_flags (bfd *abfd)
val = E_MIPS_ARCH_64 | E_MIPS_MACH_XLR;
break;
+ case bfd_mach_mips_octeon2:
+ val = E_MIPS_ARCH_64R2 | E_MIPS_MACH_OCTEON2;
+ break;
+
case bfd_mach_mipsisa32:
val = E_MIPS_ARCH_32;
break;
@@ -13492,6 +13499,7 @@ struct mips_mach_extension {
static const struct mips_mach_extension mips_mach_extensions[] = {
/* MIPS64r2 extensions. */
+ { bfd_mach_mips_octeon2, bfd_mach_mips_octeonp },
{ bfd_mach_mips_octeonp, bfd_mach_mips_octeon },
{ bfd_mach_mips_octeon, bfd_mach_mipsisa64r2 },
diff --git a/gas/ChangeLog b/gas/ChangeLog
index ebbd477ba6..472738d9df 100644
--- a/gas/ChangeLog
+++ b/gas/ChangeLog
@@ -1,3 +1,10 @@
+2011-12-08 Andrew Pinski <apinski@cavium.com>
+ Adam Nemet <anemet@caviumnetworks.com>
+
+ * tc-mips.c (CPU_IS_OCTEON): Add Octeon2.
+ (mips_cpu_info_table): Add Octeon2.
+ * doc/c-mips.texi: Document octeon2 as an acceptable value for -march=.
+
2011-12-07 Sameera Deshpande <sameera.deshpande@arm.com>
* config/tc-arm.c (do_t_ldstd): Warn for unpredictable cases.
diff --git a/gas/config/tc-mips.c b/gas/config/tc-mips.c
index 2a57393433..50e5024cb0 100644
--- a/gas/config/tc-mips.c
+++ b/gas/config/tc-mips.c
@@ -498,7 +498,7 @@ static int mips_32bitmode = 0;
#define CPU_HAS_ROR(CPU) CPU_HAS_DROR (CPU)
/* True if CPU is in the Octeon family */
-#define CPU_IS_OCTEON(CPU) ((CPU) == CPU_OCTEON || (CPU) == CPU_OCTEONP)
+#define CPU_IS_OCTEON(CPU) ((CPU) == CPU_OCTEON || (CPU) == CPU_OCTEONP || (CPU) == CPU_OCTEON2)
/* True if CPU has seq/sne and seqi/snei instructions. */
#define CPU_HAS_SEQ(CPU) (CPU_IS_OCTEON (CPU))
@@ -19075,6 +19075,7 @@ static const struct mips_cpu_info mips_cpu_info_table[] =
/* Cavium Networks Octeon CPU core */
{ "octeon", 0, ISA_MIPS64R2, CPU_OCTEON },
{ "octeon+", 0, ISA_MIPS64R2, CPU_OCTEONP },
+ { "octeon2", 0, ISA_MIPS64R2, CPU_OCTEON2 },
/* RMI Xlr */
{ "xlr", 0, ISA_MIPS64, CPU_XLR },
diff --git a/gas/doc/c-mips.texi b/gas/doc/c-mips.texi
index ddfcbd95f2..7fe9337ad4 100644
--- a/gas/doc/c-mips.texi
+++ b/gas/doc/c-mips.texi
@@ -324,6 +324,7 @@ loongson2f,
loongson3a,
octeon,
octeon+,
+octeon2,
xlr
@end quotation
diff --git a/gas/testsuite/ChangeLog b/gas/testsuite/ChangeLog
index 446f260038..5296794731 100644
--- a/gas/testsuite/ChangeLog
+++ b/gas/testsuite/ChangeLog
@@ -1,3 +1,11 @@
+2011-12-08 Andrew Pinski <apinski@cavium.com>
+ Adam Nemet <anemet@caviumnetworks.com>
+
+ * gas/mips/mips.exp: Add Octeon2 for an architecture.
+ Run octeon2 test.
+ * gas/mips/octeon2.d: New file.
+ * gas/mips/octeon2.s: New file.
+
2011-12-07 Sameera Deshpande <sameera.deshpande@arm.com>
* gas/arm/thumb2_ldstd_unpredictable.d: New testcase.
diff --git a/gas/testsuite/gas/mips/mips.exp b/gas/testsuite/gas/mips/mips.exp
index d47ebc63e6..4beb3e29a2 100644
--- a/gas/testsuite/gas/mips/mips.exp
+++ b/gas/testsuite/gas/mips/mips.exp
@@ -438,6 +438,9 @@ mips_arch_create octeon 64 mips64r2 {} \
mips_arch_create octeonp 64 octeon {} \
{ -march=octeon+ -mtune=octeon+ } { -mmips:octeon+ } \
{ }
+mips_arch_create octeon2 64 octeonp {} \
+ { -march=octeon2 -mtune=octeon2 } { -mmips:octeon2 } \
+ { }
mips_arch_create xlr 64 mips64 {} \
{ -march=xlr -mtune=xlr } { -mmips:xlr }
@@ -1016,6 +1019,7 @@ if { [istarget mips*-*-vxworks*] } {
run_dump_test_arches "octeon-saa-saad" [mips_arch_list_matching octeonp]
run_list_test_arches "octeon-ill" [mips_arch_list_matching octeon]
run_dump_test_arches "octeon-pref" [mips_arch_list_matching octeon]
+ run_dump_test_arches "octeon2" [mips_arch_list_matching octeon2]
run_dump_test "smartmips"
run_dump_test "mips32-dsp"
diff --git a/gas/testsuite/gas/mips/octeon2.d b/gas/testsuite/gas/mips/octeon2.d
new file mode 100644
index 0000000000..fd13be312a
--- /dev/null
+++ b/gas/testsuite/gas/mips/octeon2.d
@@ -0,0 +1,38 @@
+#objdump: -M reg-names=numeric -dr
+#name: MIPS octeon2 instructions
+
+.*: file format .*
+
+Disassembly of section .text:
+
+[0-9a-f]+ <foo>:
+.*: 70700412 qmac.00 \$3,\$16
+.*: 71aa0452 qmac.01 \$13,\$10
+.*: 704d0492 qmac.02 \$2,\$13
+.*: 721704d2 qmac.03 \$16,\$23
+.*: 704a0012 qmacs.00 \$2,\$10
+.*: 73ca0052 qmacs.01 \$30,\$10
+.*: 718d0092 qmacs.02 \$12,\$13
+.*: 70c600d2 qmacs.03 \$6,\$6
+.*: 7c697d8a lbx \$15,\$9\(\$3\)
+.*: 7dfc298a lbux \$5,\$28\(\$15\)
+.*: 7cd9890a lhx \$17,\$25\(\$6\)
+.*: 7c15fd0a lhux \$31,\$21\(\$0\)
+.*: 7cbda80a lwx \$21,\$29\(\$5\)
+.*: 7cc5940a lwux \$18,\$5\(\$6\)
+.*: 7efdb20a ldx \$22,\$29\(\$23\)
+.*: 722d149f laa \$2,\(\$17\),\$13
+.*: 71d03cdf laad \$7,\(\$14\),\$16
+.*: 7105d59f law \$26,\(\$8\),\$5
+.*: 71f6a5df lawd \$20,\(\$15\),\$22
+.*: 7060389f lai \$7,\(\$3\)
+.*: 7160f8df laid \$31,\(\$11\)
+.*: 73e0c99f lad \$25,\(\$31\)
+.*: 7080f1df ladd \$30,\(\$4\)
+.*: 71006a9f las \$13,\(\$8\)
+.*: 73c0dadf lasd \$27,\(\$30\)
+.* 73806b9f lac \$13,\(\$28\)
+.* 71003bdf lacd \$7,\(\$8\)
+.* 7260071f zcb \(\$19\)
+.* 7220075f zcbt \(\$17\)
+#pass
diff --git a/gas/testsuite/gas/mips/octeon2.s b/gas/testsuite/gas/mips/octeon2.s
new file mode 100644
index 0000000000..a2af362779
--- /dev/null
+++ b/gas/testsuite/gas/mips/octeon2.s
@@ -0,0 +1,38 @@
+ .text
+ .set noreorder
+ .set noat
+
+foo:
+ qmac.00 $3,$16
+ qmac.01 $13,$10
+ qmac.02 $2,$13
+ qmac.03 $16,$23
+
+ qmacs.00 $2,$10
+ qmacs.01 $30,$10
+ qmacs.02 $12,$13
+ qmacs.03 $6,$6
+
+ lbx $15,$9($3)
+ lbux $5,$28($15)
+ lhx $17,$25($6)
+ lhux $31,$21
+ lwx $21,$29($5)
+ lwux $18,$5($6)
+ ldx $22,$29($23)
+
+ laa $2,($17),$13
+ laad $7,($14),$16
+ law $26,($8),$5
+ lawd $20,($15),$22
+ lai $7,($3)
+ laid $31,($11)
+ lad $25,($31)
+ ladd $30,($4)
+ las $13,($8)
+ lasd $27,($30)
+ lac $13,($28)
+ lacd $7,($8)
+
+ zcb ($19)
+ zcbt ($17)
diff --git a/include/opcode/ChangeLog b/include/opcode/ChangeLog
index bfd71e055b..2cbb382d54 100644
--- a/include/opcode/ChangeLog
+++ b/include/opcode/ChangeLog
@@ -1,3 +1,11 @@
+2011-12-08 Andrew Pinski <apinski@cavium.com>
+ Adam Nemet <anemet@caviumnetworks.com>
+
+ * mips.h (INSN_CHIP_MASK): Update according to INSN_OCTEON2.
+ (INSN_OCTEON2): New macro.
+ (CPU_OCTEON2): New macro.
+ (OPCODE_IS_MEMBER): Add Octeon2.
+
2011-11-29 Andrew Pinski <apinski@cavium.com>
* mips.h (INSN_CHIP_MASK): Update according to INSN_OCTEONP.
diff --git a/include/opcode/mips.h b/include/opcode/mips.h
index eb28d160f3..fb9094c26f 100644
--- a/include/opcode/mips.h
+++ b/include/opcode/mips.h
@@ -713,11 +713,12 @@ static const unsigned int mips_isa_table[] =
{ 0x0001, 0x0003, 0x0607, 0x1e0f, 0x3e1f, 0x0a23, 0x3e63, 0x3ebf, 0x3fff };
/* Masks used for Chip specific instructions. */
-#define INSN_CHIP_MASK 0xc3ff0e20
+#define INSN_CHIP_MASK 0xc3ff0f20
/* Cavium Networks Octeon instructions. */
#define INSN_OCTEON 0x00000800
#define INSN_OCTEONP 0x00000200
+#define INSN_OCTEON2 0x00000100
/* Masks used for MIPS-defined ASEs. */
#define INSN_ASE_MASK 0x3c00f010
@@ -825,6 +826,7 @@ static const unsigned int mips_isa_table[] =
#define CPU_LOONGSON_3A 3003
#define CPU_OCTEON 6501
#define CPU_OCTEONP 6601
+#define CPU_OCTEON2 6502
#define CPU_XLR 887682 /* decimal 'XLR' */
/* Test for membership in an ISA including chip specific ISAs. INSN
@@ -863,6 +865,8 @@ static const unsigned int mips_isa_table[] =
&& ((insn)->membership & INSN_OCTEON) != 0) \
|| (cpu == CPU_OCTEONP \
&& ((insn)->membership & INSN_OCTEONP) != 0) \
+ || (cpu == CPU_OCTEON2 \
+ && ((insn)->membership & INSN_OCTEON2) != 0) \
|| (cpu == CPU_XLR && ((insn)->membership & INSN_XLR) != 0) \
|| 0) /* Please keep this term for easier source merging. */
diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog
index 9458f0e211..6f1ccbfa7b 100644
--- a/opcodes/ChangeLog
+++ b/opcodes/ChangeLog
@@ -1,3 +1,20 @@
+2011-12-08 Andrew Pinski <apinski@cavium.com>
+ Adam Nemet <anemet@caviumnetworks.com>
+
+ * mips-dis.c (mips_arch_choices): Add Octeon2.
+ For "octeon+", just include OcteonP for the insn.
+ * mips-opc.c (IOCT): Include Octeon2.
+ (IOCTP): Include Octeon2.
+ (IOCT2): New macro.
+ (mips_builtin_opcodes): Add "laa", "laad", "lac", "lacd", "lad",
+ "ladd", "lai", "laid", "las", "lasd", "law", "lawd".
+ Move "lbux", "ldx", "lhx", "lwx", and "lwux" up to where the standard
+ loads are, and add IOCT2 to them.
+ Add "lbx" and "lhux".
+ Add "qmac.00", "qmac.01", "qmac.02", "qmac.03", "qmacs.00",
+ "qmacs.01", "qmacs.01", "qmacs.02" and "qmacs.03".
+ Add "zcb" and "zcbt".
+
2011-11-29 Andrew Pinski <apinski@cavium.com>
* mips-dis.c (mips_arch_choices): Add Octeon+.
diff --git a/opcodes/mips-dis.c b/opcodes/mips-dis.c
index 09714ac9df..0d1de30f97 100644
--- a/opcodes/mips-dis.c
+++ b/opcodes/mips-dis.c
@@ -606,7 +606,11 @@ const struct mips_arch_choice mips_arch_choices[] =
mips_hwr_names_numeric },
{ "octeon+", 1, bfd_mach_mips_octeonp, CPU_OCTEONP,
- ISA_MIPS64R2 | INSN_OCTEON | INSN_OCTEONP, mips_cp0_names_numeric,
+ ISA_MIPS64R2 | INSN_OCTEONP, mips_cp0_names_numeric,
+ NULL, 0, mips_hwr_names_numeric },
+
+ { "octeon2", 1, bfd_mach_mips_octeon2, CPU_OCTEON2,
+ ISA_MIPS64R2 | INSN_OCTEON2, mips_cp0_names_numeric,
NULL, 0, mips_hwr_names_numeric },
{ "xlr", 1, bfd_mach_mips_xlr, CPU_XLR,
diff --git a/opcodes/mips-opc.c b/opcodes/mips-opc.c
index a0e05f52fc..ce92b120c2 100644
--- a/opcodes/mips-opc.c
+++ b/opcodes/mips-opc.c
@@ -121,8 +121,9 @@
#define N5 (INSN_5400 | INSN_5500)
#define N54 INSN_5400
#define N55 INSN_5500
-#define IOCT (INSN_OCTEON | INSN_OCTEONP)
-#define IOCTP INSN_OCTEONP
+#define IOCT (INSN_OCTEON | INSN_OCTEONP | INSN_OCTEON2)
+#define IOCTP (INSN_OCTEONP | INSN_OCTEON2)
+#define IOCT2 INSN_OCTEON2
#define XLR INSN_XLR
#define G1 (T3 \
@@ -818,10 +819,29 @@ const struct mips_opcode mips_builtin_opcodes[] =
{"jal", "a", 0x0c000000, 0xfc000000, UBD|WR_31, 0, I1 },
{"jalx", "a", 0x74000000, 0xfc000000, UBD|WR_31, 0, I1 },
{"la", "t,A(b)", 0, (int) M_LA_AB, INSN_MACRO, 0, I1 },
+{"laa", "d,(b),t", 0x7000049f, 0xfc0007ff, LDD|SM|WR_d|RD_t|RD_b, 0, IOCT2 },
+{"laad", "d,(b),t", 0x700004df, 0xfc0007ff, LDD|SM|WR_d|RD_t|RD_b, 0, IOCT2 },
+{"lac", "d,(b)", 0x7000039f, 0xfc1f07ff, LDD|SM|WR_d|RD_b, 0, IOCT2 },
+{"lacd", "d,(b)", 0x700003df, 0xfc1f07ff, LDD|SM|WR_d|RD_b, 0, IOCT2 },
+{"lad", "d,(b)", 0x7000019f, 0xfc1f07ff, LDD|SM|WR_d|RD_t|RD_b, 0, IOCT2 },
+{"ladd", "d,(b)", 0x700001df, 0xfc1f07ff, LDD|SM|WR_d|RD_t|RD_b, 0, IOCT2 },
+{"lai", "d,(b)", 0x7000009f, 0xfc1f07ff, LDD|SM|WR_d|RD_t|RD_b, 0, IOCT2 },
+{"laid", "d,(b)", 0x700000df, 0xfc1f07ff, LDD|SM|WR_d|RD_t|RD_b, 0, IOCT2 },
+{"las", "d,(b)", 0x7000029f, 0xfc1f07ff, LDD|SM|WR_d|RD_b, 0, IOCT2 },
+{"lasd", "d,(b)", 0x700002df, 0xfc1f07ff, LDD|SM|WR_d|RD_b, 0, IOCT2 },
+{"law", "d,(b),t", 0x7000059f, 0xfc0007ff, LDD|SM|WR_d|RD_t|RD_b, 0, IOCT2 },
+{"lawd", "d,(b),t", 0x700005df, 0xfc0007ff, LDD|SM|WR_d|RD_t|RD_b, 0, IOCT2 },
{"lb", "t,o(b)", 0x80000000, 0xfc000000, LDD|RD_b|WR_t, 0, I1 },
{"lb", "t,A(b)", 0, (int) M_LB_AB, INSN_MACRO, 0, I1 },
{"lbu", "t,o(b)", 0x90000000, 0xfc000000, LDD|RD_b|WR_t, 0, I1 },
{"lbu", "t,A(b)", 0, (int) M_LBU_AB, INSN_MACRO, 0, I1 },
+{"lbx", "d,t(b)", 0x7c00058a, 0xfc0007ff, LDD|WR_d|RD_t|RD_b, 0, IOCT2 },
+{"lbux", "d,t(b)", 0x7c00018a, 0xfc0007ff, LDD|WR_d|RD_t|RD_b, 0, D32|IOCT2},
+{"ldx", "d,t(b)", 0x7c00020a, 0xfc0007ff, LDD|WR_d|RD_t|RD_b, 0, D64|IOCT2},
+{"lhx", "d,t(b)", 0x7c00010a, 0xfc0007ff, LDD|WR_d|RD_t|RD_b, 0, D32|IOCT2},
+{"lhux", "d,t(b)", 0x7c00050a, 0xfc0007ff, LDD|WR_d|RD_t|RD_b, 0, IOCT2 },
+{"lwx", "d,t(b)", 0x7c00000a, 0xfc0007ff, LDD|WR_d|RD_t|RD_b, 0, D32|IOCT2},
+{"lwux", "d,t(b)", 0x7c00040a, 0xfc0007ff, LDD|WR_d|RD_t|RD_b, 0, IOCT2 },
{"lca", "t,A(b)", 0, (int) M_LCA_AB, INSN_MACRO, 0, I1 },
/* The macro has to be first to handle o32 correctly. */
{"ld", "t,o(b)", 0, (int) M_LD_OB, INSN_MACRO, 0, I1 },
@@ -1187,6 +1207,14 @@ const struct mips_opcode mips_builtin_opcodes[] =
{"pul.ps", "D,V,T", 0x46c0002e, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, 0, I5_33 },
{"puu.ps", "D,V,T", 0x46c0002f, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, 0, I5_33 },
{"pperm", "s,t", 0x70000481, 0xfc00ffff, MOD_HILO|RD_s|RD_t, 0, SMT },
+{"qmac.00", "s,t", 0x70000412, 0xfc00ffff, MOD_HILO|RD_s|RD_t, 0, IOCT2 },
+{"qmac.01", "s,t", 0x70000452, 0xfc00ffff, MOD_HILO|RD_s|RD_t, 0, IOCT2 },
+{"qmac.02", "s,t", 0x70000492, 0xfc00ffff, MOD_HILO|RD_s|RD_t, 0, IOCT2 },
+{"qmac.03", "s,t", 0x700004d2, 0xfc00ffff, MOD_HILO|RD_s|RD_t, 0, IOCT2 },
+{"qmacs.00", "s,t", 0x70000012, 0xfc00ffff, MOD_HILO|RD_s|RD_t, 0, IOCT2 },
+{"qmacs.01", "s,t", 0x70000052, 0xfc00ffff, MOD_HILO|RD_s|RD_t, 0, IOCT2 },
+{"qmacs.02", "s,t", 0x70000092, 0xfc00ffff, MOD_HILO|RD_s|RD_t, 0, IOCT2 },
+{"qmacs.03", "s,t", 0x700000d2, 0xfc00ffff, MOD_HILO|RD_s|RD_t, 0, IOCT2 },
{"rach.ob", "X", 0x7a00003f, 0xfffff83f, WR_D|FP_D, RD_MACC, MX|SB1 },
{"rach.ob", "D", 0x4a00003f, 0xfffff83f, WR_D, 0, N54 },
{"rach.qh", "X", 0x7a20003f, 0xfffff83f, WR_D|FP_D, RD_MACC, MX },
@@ -1517,6 +1545,8 @@ const struct mips_opcode mips_builtin_opcodes[] =
{"xori", "t,r,i", 0x38000000, 0xfc000000, WR_t|RD_s, 0, I1 },
{"yield", "s", 0x7c000009, 0xfc1fffff, NODS|RD_s, 0, MT32 },
{"yield", "d,s", 0x7c000009, 0xfc1f07ff, NODS|WR_d|RD_s, 0, MT32 },
+{"zcb", "(b)", 0x7000071f, 0xfc1fffff, SM|RD_b, 0, IOCT2 },
+{"zcbt", "(b)", 0x7000075f, 0xfc1fffff, SM|RD_b, 0, IOCT2 },
/* User Defined Instruction. */
{"udi0", "s,t,d,+1",0x70000010, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 },
@@ -1729,10 +1759,7 @@ const struct mips_opcode mips_builtin_opcodes[] =
{"extrv.w", "t,7,s", 0x7c000078, 0xfc00e7ff, WR_t|RD_a|RD_s, 0, D32 },
{"extr.w", "t,7,6", 0x7c000038, 0xfc00e7ff, WR_t|RD_a, 0, D32 },
{"insv", "t,s", 0x7c00000c, 0xfc00ffff, WR_t|RD_s, 0, D32 },
-{"lbux", "d,t(b)", 0x7c00018a, 0xfc0007ff, LDD|WR_d|RD_t|RD_b, 0, D32 },
-{"ldx", "d,t(b)", 0x7c00020a, 0xfc0007ff, LDD|WR_d|RD_t|RD_b, 0, D64 },
-{"lhx", "d,t(b)", 0x7c00010a, 0xfc0007ff, LDD|WR_d|RD_t|RD_b, 0, D32 },
-{"lwx", "d,t(b)", 0x7c00000a, 0xfc0007ff, LDD|WR_d|RD_t|RD_b, 0, D32 },
+/* lbux, ldx, lhx and lwx are the basic instruction section. */
{"maq_sa.w.phl", "7,s,t", 0x7c000430, 0xfc00e7ff, MOD_a|RD_s|RD_t, 0, D32 },
{"maq_sa.w.phr", "7,s,t", 0x7c0004b0, 0xfc00e7ff, MOD_a|RD_s|RD_t, 0, D32 },
{"maq_sa.w.qhll", "7,s,t", 0x7c000434, 0xfc00e7ff, MOD_a|RD_s|RD_t, 0, D64 },
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