1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
|
# sh testcase for fabs
# mach: sh
# as(sh): -defsym sim_cpu=0
.include "testutils.inc"
start
fabs_freg_b0:
single_prec
bank0
set_grs_a5a5
set_fprs_a5a5
# fabs(0.0) = 0.0.
fldi0 fr0
fabs fr0
fldi0 fr1
fcmp/eq fr0, fr1
bt .L1
fail
.L1:
# fabs(1.0) = 1.0.
fldi1 fr0
fabs fr0
fldi1 fr1
fcmp/eq fr0, fr1
bt .L2
fail
.L2:
# fabs(-1.0) = 1.0.
fldi1 fr0
fneg fr0
fabs fr0
fldi1 fr1
fcmp/eq fr0, fr1
bt .L3
fail
.L3:
test_grs_a5a5
test_fpr_a5a5 fr2
test_fpr_a5a5 fr3
test_fpr_a5a5 fr4
test_fpr_a5a5 fr5
test_fpr_a5a5 fr6
test_fpr_a5a5 fr7
test_fpr_a5a5 fr8
test_fpr_a5a5 fr9
test_fpr_a5a5 fr10
test_fpr_a5a5 fr11
test_fpr_a5a5 fr12
test_fpr_a5a5 fr13
test_fpr_a5a5 fr14
test_fpr_a5a5 fr15
fabs_dreg_b0:
# double precision tests.
set_grs_a5a5
set_fprs_a5a5
double_prec
# fabs(0.0) = 0.0.
fldi0 fr0
flds fr0, fpul
fcnvsd fpul, dr0
fabs dr0
assert_dpreg_i 0 dr0
# fabs(1.0) = 1.0.
fldi1 fr0
flds fr0, fpul
fcnvsd fpul, dr0
fabs dr0
assert_dpreg_i 1 dr0
# check.
fldi1 fr2
flds fr2, fpul
fcnvsd fpul, dr2
fcmp/eq dr0, dr2
bt .L4
fail
.L4:
# fabs(-1.0) = 1.0.
fldi1 fr0
fneg fr0
flds fr0, fpul
fcnvsd fpul, dr0
fabs dr0
assert_dpreg_i 1 dr0
# check.
fldi1 fr2
flds fr2, fpul
fcnvsd fpul, dr2
fcmp/eq dr0, dr2
bt .L5
fail
.L5:
test_grs_a5a5
assert_dpreg_i 1 dr0
assert_dpreg_i 1 dr2
test_fpr_a5a5 fr4
test_fpr_a5a5 fr5
test_fpr_a5a5 fr6
test_fpr_a5a5 fr7
test_fpr_a5a5 fr8
test_fpr_a5a5 fr9
test_fpr_a5a5 fr10
test_fpr_a5a5 fr11
test_fpr_a5a5 fr12
test_fpr_a5a5 fr13
test_fpr_a5a5 fr14
test_fpr_a5a5 fr15
pass
exit 0
|
