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//Original:/testcases/core/c_dsp32mult_pair_is/c_dsp32mult_pair_is.dsp
// Spec Reference: dsp32mult pair is
# mach: bfin
.include "testutils.inc"
start
imm32 r0, 0x8b235625;
imm32 r1, 0x93ba5127;
imm32 r2, 0xa3446725;
imm32 r3, 0x00050027;
imm32 r4, 0xb0ab6d29;
imm32 r5, 0x10ace72b;
imm32 r6, 0xc00c008d;
imm32 r7, 0xd2467029;
R1 = R0.L * R0.L, R0 = R0.L * R0.L (ISS2);
R3 = R0.L * R1.L, R2 = R0.L * R1.H (ISS2);
R5 = R1.L * R0.L, R4 = R1.H * R0.L (ISS2);
R7 = R1.L * R1.L, R6 = R1.H * R1.H (ISS2);
CHECKREG r0, 0x39F9C2B2;
CHECKREG r1, 0x39F9C2B2;
CHECKREG r2, 0xE43C0244;
CHECKREG r3, 0x1D5C8788;
CHECKREG r4, 0xE43C0244;
CHECKREG r5, 0x1D5C8788;
CHECKREG r6, 0x1A41A862;
CHECKREG r7, 0x1D5C8788;
imm32 r0, 0x5b33a635;
imm32 r1, 0x6fbe5137;
imm32 r2, 0x1324b735;
imm32 r3, 0x9006d037;
imm32 r4, 0x80abcb39;
imm32 r5, 0xb0acef3b;
imm32 r6, 0xa00c00dd;
imm32 r7, 0x12469003;
R1 = R2.L * R2.L, R0 = R2.L * R2.L (ISS2);
R3 = R2.L * R3.L, R2 = R2.L * R3.H (ISS2);
R5 = R3.L * R2.L, R4 = R3.H * R2.L (ISS2);
R7 = R3.L * R3.L, R6 = R3.H * R3.H (ISS2);
CHECKREG r0, 0x2965A1F2;
CHECKREG r1, 0x2965A1F2;
CHECKREG r2, 0x3FAE367C;
CHECKREG r3, 0x1B2CD8C6;
CHECKREG r4, 0x0B90E2A0;
CHECKREG r5, 0xEF4D87D0;
CHECKREG r6, 0x05C49F20;
CHECKREG r7, 0x0C057248;
imm32 r0, 0x1b235655;
imm32 r1, 0xc4ba5157;
imm32 r2, 0x63246755;
imm32 r3, 0x00060055;
imm32 r4, 0x90abc509;
imm32 r5, 0x10acef5b;
imm32 r6, 0xb00c005d;
imm32 r7, 0x1246705f;
R1 = R4.L * R4.L, R0 = R4.L * R4.L (ISS2);
R3 = R4.L * R5.L, R2 = R4.L * R5.H (ISS2);
R5 = R5.L * R4.L, R4 = R5.H * R4.L (ISS2);
R7 = R5.L * R5.L, R6 = R5.H * R5.H (ISS2);
CHECKREG r0, 0x1B29B4A2;
CHECKREG r1, 0x1B29B4A2;
CHECKREG r2, 0xF851E418;
CHECKREG r3, 0x07AAE266;
CHECKREG r4, 0xF851E418;
CHECKREG r5, 0x07AAE266;
CHECKREG r6, 0x007579C8;
CHECKREG r7, 0x06D88148;
imm32 r0, 0xab235666;
imm32 r1, 0xeaba5166;
imm32 r2, 0x13d48766;
imm32 r3, 0xf00b0066;
imm32 r4, 0x90ab9d69;
imm32 r5, 0x10ac5f6b;
imm32 r6, 0x800cb66d;
imm32 r7, 0x1246707f;
R1 = R6.L * R6.L, R0 = R6.L * R6.L (ISS2);
R3 = R6.L * R7.L, R2 = R6.L * R7.H (ISS2);
R5 = R7.L * R6.L, R4 = R7.H * R6.L (ISS2);
R7 = R7.L * R7.L, R6 = R7.H * R7.H (ISS2);
CHECKREG r0, 0x2A4A54D2;
CHECKREG r1, 0x2A4A54D2;
CHECKREG r2, 0xF57F179C;
CHECKREG r3, 0xBF566026;
CHECKREG r4, 0xF57F179C;
CHECKREG r5, 0xBF566026;
CHECKREG r6, 0x029BD648;
CHECKREG r7, 0x62DEBE02;
// mix order
imm32 r0, 0xab23a675;
imm32 r1, 0xcfba5127;
imm32 r2, 0x13246705;
imm32 r3, 0x00060007;
imm32 r4, 0x90abcd09;
imm32 r5, 0x10acdfdb;
imm32 r6, 0x000c000d;
imm32 r7, 0x1246f00f;
R1 = R3.L * R2.L (M), R0 = R3.L * R2.H (ISS2);
R3 = R1.L * R0.H, R2 = R1.H * R0.L (ISS2);
R5 = R7.H * R4.L, R4 = R7.H * R4.L (ISS2);
R7 = R5.L * R6.L (M), R6 = R5.H * R6.L (ISS2);
CHECKREG r0, 0x00010BF8;
CHECKREG r1, 0x0005A246;
CHECKREG r2, 0x000077B0;
CHECKREG r3, 0xFFFF448C;
CHECKREG r4, 0xF8B964EC;
CHECKREG r5, 0xF8B964EC;
CHECKREG r6, 0xFFFF42CA;
CHECKREG r7, 0x000A3FF8;
imm32 r0, 0x9b235a75;
imm32 r1, 0xc9ba5127;
imm32 r2, 0x13946905;
imm32 r3, 0x00090007;
imm32 r4, 0x90ab9d09;
imm32 r5, 0x10ace9db;
imm32 r6, 0x000c0d9d;
imm32 r7, 0x12467009;
R3 = R6.L * R5.L, R2 = R6.L * R5.H (ISS2);
R1 = R3.L * R0.H (M), R0 = R3.H * R0.L (ISS2);
R5 = R1.L * R4.L (M), R4 = R1.H * R4.L (ISS2);
R7 = R2.H * R7.L, R6 = R2.H * R7.L (ISS2);
CHECKREG r0, 0xFE55DCD2;
CHECKREG r1, 0x18FCF734;
CHECKREG r2, 0x01C5EAF8;
CHECKREG r3, 0xFDA5149E;
CHECKREG r4, 0xECAED9B8;
CHECKREG r5, 0xF53529A8;
CHECKREG r6, 0x018C7FDA;
CHECKREG r7, 0x018C7FDA;
imm32 r0, 0x8b235675;
imm32 r1, 0xc8ba5127;
imm32 r2, 0x13846705;
imm32 r3, 0x00080007;
imm32 r4, 0x90ab8d09;
imm32 r5, 0x10ace8db;
imm32 r6, 0x000c008d;
imm32 r7, 0x12467008;
R3 = R6.H * R5.L, R2 = R6.L * R5.H (ISS2);
R7 = R2.L * R0.H (M), R6 = R2.H * R0.L (ISS2);
R5 = R1.L * R3.L (M), R4 = R1.H * R3.L (ISS2);
R1 = R2.H * R7.L, R0 = R2.L * R7.H (ISS2);
CHECKREG r0, 0x4A306970;
CHECKREG r1, 0xFFFB5540;
CHECKREG r2, 0x00125D78;
CHECKREG r3, 0xFFFDD488;
CHECKREG r4, 0x12C555A0;
CHECKREG r5, 0x7FFFFFFF;
CHECKREG r6, 0x000C2874;
CHECKREG r7, 0x6599DED0;
imm32 r0, 0xeb235675;
imm32 r1, 0xceba5127;
imm32 r2, 0x13e46705;
imm32 r3, 0x000e0007;
imm32 r4, 0x90abed09;
imm32 r5, 0x10aceedb;
imm32 r6, 0x000c00ed;
imm32 r7, 0x1246700e;
R1 = R1.H * R4.L, R0 = R1.H * R4.L (ISS2);
R3 = R2.L * R5.L, R2 = R2.L * R5.H (ISS2);
R5 = R3.H * R6.L, R4 = R3.L * R6.L (ISS2);
R7 = R4.L * R0.H, R6 = R4.H * R0.L (ISS2);
CHECKREG r0, 0x074CED14;
CHECKREG r1, 0x074CED14;
CHECKREG r2, 0x0D6B0EB8;
CHECKREG r3, 0xF2338E8E;
CHECKREG r4, 0xFF2DF2EC;
CHECKREG r5, 0xFFE6726E;
CHECKREG r6, 0x001F3108;
CHECKREG r7, 0xFF412420;
pass
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