path: root/opcodes/ChangeLog

2020-06-26  Jan Beulich  <jbeulich@suse.com>

	* i386-dis.c: Adjust description of I macro.
	(x86_64_table): Drop use of I.
	(float_mem): Replace use of I.
	(putop): Remove handling of I. Adjust setting/clearing of "alt".

2020-06-26  Jan Beulich  <jbeulich@suse.com>

	* i386-dis.c: (print_insn): Avoid straight assignment to
	priv.orig_sizeflag when processing -M sub-options.

2020-06-25  Jan Beulich  <jbeulich@suse.com>

	* i386-dis.c: Adjust description of J macro.
	(dis386, x86_64_table, mod_table): Replace J.
	(putop): Remove handling of J.

2020-06-25  Jan Beulich  <jbeulich@suse.com>

	* i386-dis.c: (float_mem): Reduce alternatives for fstpt and fldpt.

2020-06-25  Jan Beulich  <jbeulich@suse.com>

	* i386-dis.c: Adjust description of "LQ" macro.
	(dis386_twobyte): Use LQ for sysret.
	(putop): Adjust handling of LQ.

2020-06-22  Nelson Chu  <nelson.chu@sifive.com>

	* riscv-opc.c: Move the structures and functions to bfd/elfxx-riscv.c.
	* riscv-dis.c: Include elfxx-riscv.h.

2020-06-18  H.J. Lu  <hongjiu.lu@intel.com>

	* i386-dis.c (prefix_table): Revert the last vmgexit change.

2020-06-17  Lili Cui  <lili.cui@intel.com>

	* i386-dis.c (prefix_table): Delete the incorrect vmgexit.

2020-06-14  H.J. Lu  <hongjiu.lu@intel.com>

	PR gas/26115
	* i386-dis.c (prefix_table): Replace xsuspldtrk with xsusldtrk.
	* i386-opc.tbl: Likewise.
	* i386-tbl.h: Regenerated.

2020-06-12  Nelson Chu  <nelson.chu@sifive.com>

	* riscv-opc.c (priv_specs): Remove v1.9 and PRIV_SPEC_CLASS_1P9.

2020-06-11  Alex Coplan  <alex.coplan@arm.com>

	* aarch64-opc.c (SYSREG): New macro for describing system registers.
	(SR_CORE): Likewise.
	(SR_FEAT): Likewise.
	(SR_RNG): Likewise.
	(SR_V8_1): Likewise.
	(SR_V8_2): Likewise.
	(SR_V8_3): Likewise.
	(SR_V8_4): Likewise.
	(SR_PAN): Likewise.
	(SR_RAS): Likewise.
	(SR_SSBS): Likewise.
	(SR_SVE): Likewise.
	(SR_ID_PFR2): Likewise.
	(SR_PROFILE): Likewise.
	(SR_MEMTAG): Likewise.
	(SR_SCXTNUM): Likewise.
	(aarch64_sys_regs): Refactor to store feature information in the table.
	(aarch64_sys_reg_supported_p): Collapse logic for system registers
	that now describe their own features.
	(aarch64_pstatefield_supported_p): Likewise.

2020-06-09  H.J. Lu  <hongjiu.lu@intel.com>

	* i386-dis.c (prefix_table): Fix a typo in comments.

2020-06-09  Jan Beulich  <jbeulich@suse.com>

	* i386-dis.c (rex_ignored): Delete.
	(ckprefix): Drop rex_ignored initialization.
	(get_valid_dis386): Drop setting of rex_ignored.
	(print_insn): Drop checking of rex_ignored. Don't record data
	size prefix as used with VEX-and-alike encodings.

2020-06-09  Jan Beulich  <jbeulich@suse.com>

	* i386-dis.c (MOD_0F12_PREFIX_2, MOD_0F16_PREFIX_2,
	MOD_VEX_0F12_PREFIX_2, MOD_VEX_0F16_PREFIX_2): New enumerators.
	(VEX_LEN_0F12_P_2, VEX_LEN_0F16_P_2): Delete.
	(VEX_LEN_0F12_P_2_M_0, VEX_LEN_0F16_P_2_M_0): Define.
	(prefix_table): Decode MOD for cases 2 of opcodes 0F12, 0F16,
	VEX_0F12, and VEX_0F16.
	(vex_len_table): Use X for vmovlp* and vmovh*s. Drop
	VEX_LEN_0F12_P_2 and VEX_LEN_0F16_P_2 entries.
	(mod_table): Use X for movlpX and movhpX. Drop PREFIX_OPCODE
	from movlps and movhlps. New MOD_0F12_PREFIX_2,
	MOD_0F16_PREFIX_2, MOD_VEX_0F12_PREFIX_2, and
	MOD_VEX_0F16_PREFIX_2 entries.

2020-06-09  Jan Beulich  <jbeulich@suse.com>

	* i386-dis.c (MOD_EVEX_0F12_PREFIX_2, MOD_EVEX_0F13,
	MOD_EVEX_0F16_PREFIX_2, MOD_EVEX_0F17, MOD_EVEX_0F2B): New enumerators.
	(PREFIX_EVEX_0F13, PREFIX_EVEX_0F14, PREFIX_EVEX_0F15,
	PREFIX_EVEX_0F17, PREFIX_EVEX_0F28, PREFIX_EVEX_0F29,
	PREFIX_EVEX_0F2B, PREFIX_EVEX_0F54, PREFIX_EVEX_0F55,
	PREFIX_EVEX_0F56, PREFIX_EVEX_0F57, PREFIX_EVEX_0FC6,
	EVEX_W_0F10_P_0, EVEX_W_0F10_P_2, EVEX_W_0F11_P_0,
	EVEX_W_0F11_P_2, EVEX_W_0F12_P_0_M_0, EVEX_W_0F12_P_2,
	EVEX_W_0F13_P_0, EVEX_W_0F13_P_2, EVEX_W_0F14_P_0,
	EVEX_W_0F14_P_2, EVEX_W_0F15_P_0, EVEX_W_0F15_P_2,
	EVEX_W_0F16_P_0_M_0, EVEX_W_0F16_P_2, EVEX_W_0F17_P_0,
	EVEX_W_0F17_P_2, EVEX_W_0F28_P_0, EVEX_W_0F28_P_2,
	EVEX_W_0F29_P_0, EVEX_W_0F29_P_2, EVEX_W_0F2B_P_0,
	EVEX_W_0F2B_P_2, EVEX_W_0F2E_P_0, EVEX_W_0F2E_P_2,
	EVEX_W_0F2F_P_0, EVEX_W_0F2F_P_2, EVEX_W_0F51_P_0,
	EVEX_W_0F51_P_2, EVEX_W_0F54_P_0, EVEX_W_0F54_P_2,
	EVEX_W_0F55_P_0, EVEX_W_0F55_P_2, EVEX_W_0F56_P_0,
	EVEX_W_0F56_P_2, EVEX_W_0F57_P_0, EVEX_W_0F57_P_2,
	EVEX_W_0F58_P_0, EVEX_W_0F58_P_2, EVEX_W_0F59_P_0,
	EVEX_W_0F59_P_2, EVEX_W_0F5C_P_0, EVEX_W_0F5C_P_2,
	EVEX_W_0F5D_P_0, EVEX_W_0F5D_P_2, EVEX_W_0F5E_P_0,
	EVEX_W_0F5E_P_2, EVEX_W_0F5F_P_0, EVEX_W_0F5F_P_2,
	EVEX_W_0FC2_P_0, EVEX_W_0FC2_P_2, EVEX_W_0FC6_P_0,
	EVEX_W_0FC6_P_2): Delete.
	(print_insn): Add EVEX.W vs embedded prefix consistency check
	to prefix validation.
	* i386-dis-evex.h (evex_table): Don't further descend for
	vunpcklpX, vunpckhpX, vmovapX, vandpX, vandnpX, vorpX, vxorpX,
	and vshufpX. Continue with MOD decoding for opcodes 0F13, 0F17,
	and 0F2B.
	* i386-dis-evex-mod.h: Add/adjust vmovlpX/vmovhpX entries.
	* i386-dis-evex-prefix.h: Don't further descend for vmovupX,
	vucomisX, vcomisX, vsqrtpX, vaddpX, vmulpX, vsubpX, vminpX,
	vdivpX, vmaxpX, and vcmppX. Continue with MOD decoding for cases
	2 of PREFIX_EVEX_0F12, PREFIX_EVEX_0F16, and PREFIX_EVEX_0F29.
	Drop PREFIX_EVEX_0F13, PREFIX_EVEX_0F14, PREFIX_EVEX_0F15,
	PREFIX_EVEX_0F17, PREFIX_EVEX_0F28, PREFIX_EVEX_0F2B,
	PREFIX_EVEX_0F54, PREFIX_EVEX_0F55, PREFIX_EVEX_0F56,
	PREFIX_EVEX_0F57, and PREFIX_EVEX_0FC6 entries.
	* i386-dis-evex-w.h: Drop EVEX_W_0F10_P_0, EVEX_W_0F10_P_2,
	EVEX_W_0F11_P_0, EVEX_W_0F11_P_2, EVEX_W_0F12_P_0_M_0,
	EVEX_W_0F12_P_2, EVEX_W_0F12_P_3, EVEX_W_0F13_P_0,
	EVEX_W_0F13_P_2, EVEX_W_0F14_P_0, EVEX_W_0F14_P_2,
	EVEX_W_0F15_P_0, EVEX_W_0F15_P_2, EVEX_W_0F16_P_0_M_0,
	EVEX_W_0F16_P_2, EVEX_W_0F17_P_0, EVEX_W_0F17_P_2,
	EVEX_W_0F28_P_0, EVEX_W_0F28_P_2, EVEX_W_0F29_P_0,
	EVEX_W_0F29_P_2, EVEX_W_0F2B_P_0, EVEX_W_0F2B_P_2,
	EVEX_W_0F2E_P_0, EVEX_W_0F2E_P_2, EVEX_W_0F2F_P_0,
	EVEX_W_0F2F_P_2, EVEX_W_0F51_P_0, EVEX_W_0F51_P_2,
	EVEX_W_0F54_P_0, EVEX_W_0F54_P_2, EVEX_W_0F55_P_0,
	EVEX_W_0F55_P_2, EVEX_W_0F56_P_0, EVEX_W_0F56_P_2,
	EVEX_W_0F57_P_0, EVEX_W_0F57_P_2, EVEX_W_0F58_P_0,
	EVEX_W_0F58_P_2, EVEX_W_0F59_P_0, EVEX_W_0F59_P_2,
	EVEX_W_0F5C_P_0, EVEX_W_0F5C_P_2, EVEX_W_0F5D_P_0,
	EVEX_W_0F5D_P_2, EVEX_W_0F5E_P_0, EVEX_W_0F5E_P_2,
	EVEX_W_0F5F_P_0, EVEX_W_0F5F_P_2, EVEX_W_0FC2_P_0,
	EVEX_W_0FC2_P_2, EVEX_W_0FC6_P_0, and EVEX_W_0FC6_P_2 entries.

2020-06-09  Jan Beulich  <jbeulich@suse.com>

	* i386-dis.c (vex_table): Use PREFIX_OPCODE for vunpcklpX,
	vunpckhpX, vmovapX, vandpX, vandnpX, vorpX, vxorpX and vshufpX.
	(vex_len_table) : Likewise for vmovlpX, vmovhpX, vmovntpX, and
	vmovmskpX.
	(print_insn): Drop pointless check against bad_opcode. Split
	prefix validation into legacy and VEX-and-alike parts.
	(putop): Re-work 'X' macro handling.

2020-06-09  Jan Beulich  <jbeulich@suse.com>

	* i386-dis.c (MOD_0F51): Rename to ...
	(MOD_0F50): ... this.

2020-06-08  Alex Coplan  <alex.coplan@arm.com>

	* arm-dis.c (arm_opcodes): Add dfb.
	(thumb32_opcodes): Add dfb.

2020-06-08  Jan Beulich  <jbeulich@suse.com>

	* i386-opc.h (reg_entry): Const-qualify reg_name field.

2020-06-06  Alan Modra  <amodra@gmail.com>

	* ppc-dis.c (ppc_opts): Accept -mpwr10/-Mpwr10.

2020-06-05  Alan Modra  <amodra@gmail.com>

	* cgen-dis.c (hash_insn_array): Increase size of buf.  Assert
	size is large enough.

2020-06-04  Jose E. Marchesi  <jose.marchesi@oracle.com>

	* disassemble.c (disassemble_init_for_target): Set endian_code for
	bpf targets.
	* bpf-desc.c: Regenerate.
	* bpf-opc.c: Likewise.
	* bpf-dis.c: Likewise.

2020-06-03  Jose E. Marchesi  <jose.marchesi@oracle.com>

	* cgen-opc.c (cgen_get_insn_value): Get an `endian' argument.
	(cgen_put_insn_value): Likewise.
	(cgen_lookup_insn): Pass endianness to cgen_{get,put}_insn_value.
	* cgen-dis.in (print_insn): Likewise.
	* cgen-ibld.in (insert_1): Likewise.
	(insert_1): Likewise.
	(insert_insn_normal): Likewise.
	(extract_1): Likewise.
	* bpf-dis.c: Regenerate.
	* bpf-ibld.c: Likewise.
	* bpf-ibld.c: Likewise.
	* cgen-dis.in: Likewise.
	* cgen-ibld.in: Likewise.
	* cgen-opc.c: Likewise.
	* epiphany-dis.c: Likewise.
	* epiphany-ibld.c: Likewise.
	* fr30-dis.c: Likewise.
	* fr30-ibld.c: Likewise.
	* frv-dis.c: Likewise.
	* frv-ibld.c: Likewise.
	* ip2k-dis.c: Likewise.
	* ip2k-ibld.c: Likewise.
	* iq2000-dis.c: Likewise.
	* iq2000-ibld.c: Likewise.
	* lm32-dis.c: Likewise.
	* lm32-ibld.c: Likewise.
	* m32c-dis.c: Likewise.
	* m32c-ibld.c: Likewise.
	* m32r-dis.c: Likewise.
	* m32r-ibld.c: Likewise.
	* mep-dis.c: Likewise.
	* mep-ibld.c: Likewise.
	* mt-dis.c: Likewise.
	* mt-ibld.c: Likewise.
	* or1k-dis.c: Likewise.
	* or1k-ibld.c: Likewise.
	* xc16x-dis.c: Likewise.
	* xc16x-ibld.c: Likewise.
	* xstormy16-dis.c: Likewise.
	* xstormy16-ibld.c: Likewise.

2020-06-04  Jose E. Marchesi  <jemarch@gnu.org>

	* cgen-dis.in (cpu_desc_list): New field `insn_endian'.
	(print_insn_): Handle instruction endian.
	* bpf-dis.c: Regenerate.
	* bpf-desc.c: Regenerate.
	* epiphany-dis.c: Likewise.
	* epiphany-desc.c: Likewise.
	* fr30-dis.c: Likewise.
	* fr30-desc.c: Likewise.
	* frv-dis.c: Likewise.
	* frv-desc.c: Likewise.
	* ip2k-dis.c: Likewise.
	* ip2k-desc.c: Likewise.
	* iq2000-dis.c: Likewise.
	* iq2000-desc.c: Likewise.
	* lm32-dis.c: Likewise.
	* lm32-desc.c: Likewise.
	* m32c-dis.c: Likewise.
	* m32c-desc.c: Likewise.
	* m32r-dis.c: Likewise.
	* m32r-desc.c: Likewise.
	* mep-dis.c: Likewise.
	* mep-desc.c: Likewise.
	* mt-dis.c: Likewise.
	* mt-desc.c: Likewise.
	* or1k-dis.c: Likewise.
	* or1k-desc.c: Likewise.
	* xc16x-dis.c: Likewise.
	* xc16x-desc.c: Likewise.
	* xstormy16-dis.c: Likewise.
	* xstormy16-desc.c: Likewise.

2020-06-03  Nick Clifton  <nickc@redhat.com>

	* po/sr.po: Updated Serbian translation.

2020-06-03  Nelson Chu  <nelson.chu@sifive.com>

	* riscv-opc.c (riscv_get_isa_spec_class): Change bfd_boolean to int.
	(riscv_get_priv_spec_class): Likewise.

2020-06-01  Alan Modra  <amodra@gmail.com>

	* bpf-desc.c: Regenerate.

2020-05-28  Jose E. Marchesi  <jose.marchesi@oracle.com>
	    David Faust <david.faust@oracle.com>

	* bpf-desc.c: Regenerate.
	* bpf-opc.h: Likewise.
	* bpf-opc.c: Likewise.
	* bpf-dis.c: Likewise.

2020-05-28  Alan Modra  <amodra@gmail.com>

	* nios2-dis.c (nios2_print_insn_arg): Avoid shift left of negative
	values.

2020-05-28  Alan Modra  <amodra@gmail.com>

	* ns32k-dis.c (print_insn_arg): Handle d value of 'f' for
	immediates.
	(print_insn_ns32k): Revert last change.

2020-05-28  Nick Clifton  <nickc@redhat.com>

	* ns32k-dis.c (print_insn_ns32k): Change the arg_bufs array to
	static.

2020-05-26  Sandra Loosemore  <sandra@codesourcery.com>

	Fix extraction of signed constants in nios2 disassembler (again).

	* nios2-dis.c (nios2_print_insn_arg): Add explicit casts to
	extractions of signed fields.

2020-05-26  Stefan Schulze Frielinghaus  <stefansf@linux.ibm.com>

	* s390-opc.txt: Relocate vector load/store instructions with
	additional alignment parameter and change architecture level
	constraint from z14 to z13.

2020-05-21  Alan Modra  <amodra@gmail.com>

	* arc-ext.c: Replace "if (x) free (x)" with "free (x)" throughout.
	* sparc-dis.c: Likewise.
	* tic4x-dis.c: Likewise.
	* xtensa-dis.c: Likewise.
	* bpf-desc.c: Regenerate.
	* epiphany-desc.c: Regenerate.
	* fr30-desc.c: Regenerate.
	* frv-desc.c: Regenerate.
	* ip2k-desc.c: Regenerate.
	* iq2000-desc.c: Regenerate.
	* lm32-desc.c: Regenerate.
	* m32c-desc.c: Regenerate.
	* m32r-desc.c: Regenerate.
	* mep-asm.c: Regenerate.
	* mep-desc.c: Regenerate.
	* mt-desc.c: Regenerate.
	* or1k-desc.c: Regenerate.
	* xc16x-desc.c: Regenerate.
	* xstormy16-desc.c: Regenerate.

2020-05-20  Nelson Chu  <nelson.chu@sifive.com>

	* riscv-opc.c (riscv_ext_version_table): The table used to store
	all information about the supported spec and the corresponding ISA
	versions.  Currently, only Zicsr is supported to verify the
	correctness of Z sub extension settings.  Others will be supported
	in the future patches.
	(struct isa_spec_t, isa_specs): List for all supported ISA spec
	classes and the corresponding strings.
	(riscv_get_isa_spec_class): New function.  Get the corresponding ISA
	spec class by giving a ISA spec string.
	* riscv-opc.c (struct priv_spec_t): New structure.
	(struct priv_spec_t priv_specs): List for all supported privilege spec
	classes and the corresponding strings.
	(riscv_get_priv_spec_class): New function.  Get the corresponding
	privilege spec class by giving a spec string.
	(riscv_get_priv_spec_name): New function.  Get the corresponding
	privilege spec string by giving a CSR version class.
	* riscv-dis.c: Updated since DECLARE_CSR is changed.
	* riscv-dis.c: Add new disassembler option -Mpriv-spec to dump the CSR
	according to the chosen version.  Build a hash table riscv_csr_hash to
	store the valid CSR for the chosen pirv verison.  Dump the direct
	CSR address rather than it's name if it is invalid.
	(parse_riscv_dis_option_without_args): New function.  Parse the options
	without arguments.
	(parse_riscv_dis_option): Call parse_riscv_dis_option_without_args to
	parse the options without arguments first, and then handle the options
	with arguments.  Add the new option -Mpriv-spec, which has argument.
	* riscv-dis.c (print_riscv_disassembler_options): Add description
	about the new OBJDUMP option.

2020-05-19  Peter Bergner  <bergner@linux.ibm.com>

	* ppc-opc.c (insert_ls, extract_ls): Handle 3-bit L fields and new
	WC values on POWER10 sync, dcbf  and wait instructions.
	(insert_pl, extract_pl): New functions.
	(L2OPT, LS, WC): Use insert_ls and extract_ls.
	(LS3): New , 3-bit L for sync.
	(LS3, L3OPT): New, 3-bit L for sync and dcbf.
	(SC2, PL): New, 2-bit SC and PL for sync and wait.
	(XWCPL_MASK, XL3RT_MASK, XSYNCLS_MASK): New instruction masks.
	(XOPL3, XWCPL, XSYNCLS): New opcode macros.
	(powerpc_opcodes) <dcbflp, dcbfps, dcbstps pause_short, phwsync,
	plwsync, stcisync, stncisync, stsync, waitrsv>: New extended mnemonics.
	<wait>: Enable PL operand on POWER10.
	<dcbf>: Enable L3OPT operand on POWER10.
	<sync>: Enable SC2 operand on POWER10.

2020-05-19  Stafford Horne  <shorne@gmail.com>

	PR 25184
	* or1k-asm.c: Regenerate.
	* or1k-desc.c: Regenerate.
	* or1k-desc.h: Regenerate.
	* or1k-dis.c: Regenerate.
	* or1k-ibld.c: Regenerate.
	* or1k-opc.c: Regenerate.
	* or1k-opc.h: Regenerate.
	* or1k-opinst.c: Regenerate.

2020-05-11  Alan Modra  <amodra@gmail.com>

	* ppc-opc (powerpc_opcodes): Add xscmpeqqp, xscmpgeqp, xscmpgtqp,
	xsmaxcqp, xsmincqp.

2020-05-11  Alan Modra  <amodra@gmail.com>

	* ppc-opc.c (powerpc_opcodes): Add lxvrbx, lxvrhx, lxvrwx, lxvrdx,
	stxvrbx, stxvrhx, stxvrwx, stxvrdx.

2020-05-11  Alan Modra  <amodra@gmail.com>

	* ppc-opc.c (powerpc_opcodes): Add xvtlsbb.

2020-05-11  Alan Modra  <amodra@gmail.com>

	* ppc-opc.c (powerpc_opcodes): Add vstribl, vstribr, vstrihl, vstrihr,
	vclrlb, vclrrb, vstribl., vstribr., vstrihl., vstrihr..

2020-05-11  Peter Bergner  <bergner@linux.ibm.com>

	* ppc-opc.c (powerpc_opcodes) <setbc, setbcr, setnbc, setnbcr>: New
	mnemonics.

2020-05-11  Alan Modra  <amodra@gmail.com>

	* ppc-opc.c (UIM8, P_U8XX4_MASK): Define.
	(powerpc_opcodes): Add vgnb, vcfuged, vpextd, vpdepd, vclzdm,
	vctzdm, cntlzdm, pdepd, pextd, cfuged, cnttzdm.
	(prefix_opcodes): Add xxeval.

2020-05-11  Alan Modra  <amodra@gmail.com>

	* ppc-opc.c (powerpc_opcodes): Add xxgenpcvbm, xxgenpcvhm,
	xxgenpcvwm, xxgenpcvdm.

2020-05-11  Alan Modra  <amodra@gmail.com>

	* ppc-opc.c (MP, VXVAM_MASK): Define.
	(VXVAPS_MASK): Use VXVA_MASK.
	(powerpc_opcodes): Add mtvsrbmi, vexpandbm, vexpandhm, vexpandwm,
	vexpanddm, vexpandqm, vextractbm, vextracthm, vextractwm,
	vextractdm, vextractqm, mtvsrbm, mtvsrhm, mtvsrwm, mtvsrdm, mtvsrqm,
	vcntmbb, vcntmbh, vcntmbw, vcntmbd.

2020-05-11  Alan Modra  <amodra@gmail.com>
	    Peter Bergner  <bergner@linux.ibm.com>

	* ppc-opc.c (insert_xa6a, extract_xa6a, insert_xb6a, extract_xb6a):
	New functions.
	(powerpc_operands): Define ACC, PMSK8, PMSK4, PMSK2, XMSK, YMSK,
	YMSK2, XA6a, XA6ap, XB6a entries.
	(PMMIRR, P_X_MASK, P_XX1_MASK, P_GER_MASK): Define
	(P_GER2_MASK, P_GER4_MASK, P_GER8_MASK, P_GER64_MASK): Define.
	(PPCVSX4): Define.
	(powerpc_opcodes): Add xxmfacc, xxmtacc, xxsetaccz,
	xvi8ger4pp, xvi8ger4, xvf16ger2pp, xvf16ger2, xvf32gerpp, xvf32ger,
	xvi4ger8pp, xvi4ger8, xvi16ger2spp, xvi16ger2s, xvbf16ger2pp,
	xvbf16ger2, xvf64gerpp, xvf64ger, xvi16ger2, xvf16ger2np,
	xvf32gernp, xvi8ger4spp, xvi16ger2pp, xvbf16ger2np, xvf64gernp,
	xvf16ger2pn, xvf32gerpn, xvbf16ger2pn, xvf64gerpn, xvf16ger2nn,
	xvf32gernn, xvbf16ger2nn, xvf64gernn, xvcvbf16sp, xvcvspbf16.
	(prefix_opcodes): Add pmxvi8ger4pp, pmxvi8ger4, pmxvf16ger2pp,
	pmxvf16ger2, pmxvf32gerpp, pmxvf32ger, pmxvi4ger8pp, pmxvi4ger8,
	pmxvi16ger2spp, pmxvi16ger2s, pmxvbf16ger2pp, pmxvbf16ger2,
	pmxvf64gerpp, pmxvf64ger, pmxvi16ger2, pmxvf16ger2np, pmxvf32gernp,
	pmxvi8ger4spp, pmxvi16ger2pp, pmxvbf16ger2np, pmxvf64gernp,
	pmxvf16ger2pn, pmxvf32gerpn, pmxvbf16ger2pn, pmxvf64gerpn,
	pmxvf16ger2nn, pmxvf32gernn, pmxvbf16ger2nn, pmxvf64gernn.

2020-05-11  Alan Modra  <amodra@gmail.com>

	* ppc-opc.c (insert_imm32, extract_imm32): New functions.
	(insert_xts, extract_xts): New functions.
	(IMM32, UIM3, IX, UIM5, SH3, XTS, P8RR): Define.
	(P_XX4_MASK, P_UXX4_MASK, VSOP, P_VS_MASK, P_VSI_MASK): Define.
	(VXRC_MASK, VXSH_MASK): Define.
	(powerpc_opcodes): Add vinsbvlx, vsldbi, vextdubvlx, vextdubvrx,
	vextduhvlx, vextduhvrx, vextduwvlx, vextduwvrx, vextddvlx,
	vextddvrx, vinshvlx, vinswvlx, vinsw, vinsbvrx, vinshvrx,
	vinswvrx, vinsd, vinsblx, vsrdbi, vinshlx, vinswlx, vinsdlx,
	vinsbrx, vinshrx, vinswrx, vinsdrx, lxvkq.
	(prefix_opcodes): Add xxsplti32dx, xxspltidp, xxspltiw, xxblendvb,
	xxblendvh, xxblendvw, xxblendvd, xxpermx.

2020-05-11  Alan Modra  <amodra@gmail.com>

	* ppc-opc.c (powerpc_opcodes): Add vrlq, vdivuq, vmsumcud, vrlqmi,
	vmuloud, vcmpuq, vslq, vdivsq, vcmpsq, vrlqnm, vcmpequq, vmulosd,
	vsrq, vdiveuq, vcmpgtuq, vmuleud, vsraq, vdivesq, vcmpgtsq, vmulesd,
	vcmpequq., vextsd2q, vmoduq, vcmpgtuq., vmodsq, vcmpgtsq., xscvqpuqz,
	xscvuqqp, xscvqpsqz, xscvsqqp, dcffixqq, dctfixqq.

2020-05-11  Alan Modra  <amodra@gmail.com>

	* ppc-opc.c (insert_xtp, extract_xtp): New functions.
	(XTP, DQXP, DQXP_MASK): Define.
	(powerpc_opcodes): Add lxvp, stxvp, lxvpx, stxvpx.
	(prefix_opcodes): Add plxvp and pstxvp.

2020-05-11  Alan Modra  <amodra@gmail.com>

	* ppc-opc.c (powerpc_opcodes): Add vdivuw, vdivud, vdivsw, vmulld,
	vdivsd, vmulhuw, vdiveuw, vmulhud, vdiveud, vmulhsw, vdivesw,
	vmulhsd, vdivesd, vmoduw, vmodud, vmodsw, vmodsd.

2020-05-11  Peter Bergner  <bergner@linux.ibm.com>

	* ppc-opc.c (powerpc_opcodes) <brd, brh, brw>: New mnemonics.

2020-05-11  Peter Bergner  <bergner@linux.ibm.com>

	* ppc-opc.c (insert_l1opt, extract_l1opt): New functions.
	(L1OPT): Define.
	(powerpc_opcodes) <paste.>: Add L operand for cpu POWER10.

2020-05-11  Peter Bergner  <bergner@linux.ibm.com>

	* ppc-opc.c (powerpc_opcodes) <slbiag>: Add variant with L operand.

2020-05-11  Alan Modra  <amodra@gmail.com>

	* ppc-dis.c (powerpc_init_dialect): Default to "power10".

2020-05-11  Alan Modra  <amodra@gmail.com>

	* ppc-dis.c (ppc_opts): Add "power10" entry.
	(print_insn_powerpc): Update for PPC_OPCODE_POWER10 renaming.
	* ppc-opc.c (POWER10): Rename from POWERXX.  Update all uses.

2020-05-11  Nick Clifton  <nickc@redhat.com>

	* po/fr.po: Updated French translation.

2020-04-30  Alex Coplan  <alex.coplan@arm.com>

	* aarch64-opc.h (enum aarch64_field_kind): Add FLD_imm16_2.
	* aarch64-opc.c (fields): Add entry for FLD_imm16_2.
	(operand_general_constraint_met_p): validate
	AARCH64_OPND_UNDEFINED.
	* aarch64-tbl.h (aarch64_opcode_table): Add udf instruction, entry
	for FLD_imm16_2.
	* aarch64-asm-2.c: Regenerated.
	* aarch64-dis-2.c: Regenerated.
	* aarch64-opc-2.c: Regenerated.

2020-04-29  Nick Clifton  <nickc@redhat.com>

	PR 22699
	* sh-opc.h: Also use unsigned 8-bit immediate values for the LDRC
	and SETRC insns.

2020-04-29  Nick Clifton  <nickc@redhat.com>

	* po/sv.po: Updated Swedish translation.

2020-04-29  Nick Clifton  <nickc@redhat.com>

	PR 22699
	* sh-opc.h (IMM0_8): Replace with IMM0_8S and IMM0_8U.  Use
	IMM0_8S for arithmetic insns and IMM0_8U for logical insns.
	* sh-dis.c (print_insn_sh): Change IMM0_8 case to IMM0_8S and add
	IMM0_8U case.

2020-04-21  Andreas Schwab  <schwab@linux-m68k.org>

	PR 25848
	* m68k-opc.c (m68k_opcodes): Allow pc-rel for second operand of
	cmpi only on m68020up and cpu32.

2020-04-20  Sudakshina Das  <sudi.das@arm.com>

	* aarch64-asm.c (aarch64_ins_none): New.
	* aarch64-asm.h (ins_none): New declaration.
	* aarch64-dis.c (aarch64_ext_none): New.
	* aarch64-dis.h (ext_none): New declaration.
	* aarch64-opc.c (aarch64_print_operand): Update case for
	AARCH64_OPND_BARRIER_PSB.
	* aarch64-tbl.h (aarch64_opcode_table): Add tsb.
	(AARCH64_OPERANDS): Update inserter/extracter for
	AARCH64_OPND_BARRIER_PSB to use new dummy functions.
	* aarch64-asm-2.c: Regenerated.
	* aarch64-dis-2.c: Regenerated.
	* aarch64-opc-2.c: Regenerated.

2020-04-20  Sudakshina Das  <sudi.das@arm.com>

	* aarch64-tbl.h (aarch64_feature_bti, BTI, BTI_INSN): Remove.
	(aarch64_feature_ras, RAS): Likewise.
	(aarch64_feature_stat_profile, STAT_PROFILE): Likewise.
	(aarch64_opcode_table): Update bti, xpaclri, pacia1716, pacib1716,
	autia1716, autib1716, esb, psb, dgh, paciaz, paciasp, pacibz, pacibsp,
	autiaz, autiasp, autibz, autibsp to be CORE_INSN.
	* aarch64-asm-2.c: Regenerated.
	* aarch64-dis-2.c: Regenerated.
	* aarch64-opc-2.c: Regenerated.

2020-04-17  Fredrik Strupe  <fredrik@strupe.net>

	* arm-dis.c (neon_opcodes): Fix VDUP instruction masks.
	(print_insn_neon): Support disassembly of conditional
	instructions.

2020-02-16  David Faust  <david.faust@oracle.com>

	* bpf-desc.c: Regenerate.
	* bpf-desc.h: Likewise.
	* bpf-opc.c: Regenerate.
	* bpf-opc.h: Likewise.

2020-04-07  Lili Cui  <lili.cui@intel.com>

	* i386-dis.c (enum): Add PREFIX_0F01_REG_5_MOD_3_RM_1,
	(prefix_table): New instructions (see prefixes above).
	(rm_table): Likewise
	* i386-gen.c (cpu_flag_init): Add CPU_TSXLDTRK_FLAGS,
	CPU_ANY_TSXLDTRK_FLAGS.
	(cpu_flags): Add CpuTSXLDTRK.
	* i386-opc.h (enum): Add CpuTSXLDTRK.
	(i386_cpu_flags): Add cputsxldtrk.
	* i386-opc.tbl: Add XSUSPLDTRK insns.
	* i386-init.h: Regenerate.
	* i386-tbl.h: Likewise.

2020-04-02  Lili Cui  <lili.cui@intel.com>

	* i386-dis.c (prefix_table): New instructions serialize.
	* i386-gen.c (cpu_flag_init): Add CPU_SERIALIZE_FLAGS,
	CPU_ANY_SERIALIZE_FLAGS.
	(cpu_flags): Add CpuSERIALIZE.
	* i386-opc.h (enum): Add CpuSERIALIZE.
	(i386_cpu_flags): Add cpuserialize.
	* i386-opc.tbl: Add SERIALIZE insns.
	* i386-init.h: Regenerate.
	* i386-tbl.h: Likewise.

2020-03-26  Alan Modra  <amodra@gmail.com>

	* disassemble.h (opcodes_assert): Declare.
	(OPCODES_ASSERT): Define.
	* disassemble.c: Don't include assert.h.  Include opintl.h.
	(opcodes_assert): New function.
	* h8300-dis.c (bfd_h8_disassemble_init): Use OPCODES_ASSERT.
	(bfd_h8_disassemble): Reduce size of data array.  Correctly
	calculate maxlen.  Omit insn decoding when insn length exceeds
	maxlen.  Exit from nibble loop when looking for E, before
	accessing next data byte.  Move processing of E outside loop.
	Replace tests of maxlen in loop with assertions.

2020-03-26  Alan Modra  <amodra@gmail.com>

	* arc-dis.c (find_format): Init needs_limm.  Simplify use of limm.

2020-03-25  Alan Modra  <amodra@gmail.com>

	* z80-dis.c (suffix): Init mybuf.

2020-03-22  Alan Modra  <amodra@gmail.com>

	* h8300-dis.c (bfd_h8_disassemble): Limit data[] access to that
	successflly read from section.

2020-03-22  Alan Modra  <amodra@gmail.com>

	* arc-dis.c (find_format): Use ISO C string concatenation rather
	than line continuation within a string.  Don't access needs_limm
	before testing opcode != NULL.

2020-03-22  Alan Modra  <amodra@gmail.com>

	* ns32k-dis.c (print_insn_arg): Update comment.
	(print_insn_ns32k): Reduce size of index_offset array, and
	initialize, passing -1 to print_insn_arg for args that are not
	an index.  Don't exit arg loop early.  Abort on bad arg number.

2020-03-22  Alan Modra  <amodra@gmail.com>

	* s12z-dis.c (abstract_read_memory): Don't print error on EOI.
	* s12z-opc.c: Formatting.
	(operands_f): Return an int.
	(opr_n_bytes_p1): Return -1 on reaching buffer memory limit.
	(opr_n_bytes2, bfextins_n_bytes, mul_n_bytes, bm_n_bytes),
	(shift_n_bytes, mov_imm_opr_n_bytes, loop_prim_n_bytes),
	(exg_sex_discrim): Likewise.
	(create_immediate_operand, create_bitfield_operand),
	(create_register_operand_with_size, create_register_all_operand),
	(create_register_all16_operand, create_simple_memory_operand),
	(create_memory_operand, create_memory_auto_operand): Don't
	segfault on malloc failure.
	(z_ext24_decode): Return an int status, negative on fail, zero
	on success.
	(x_imm1, imm1_decode, trap_decode, z_opr_decode, z_opr_decode2),
	(imm1234, reg_s_imm, reg_s_opr, z_imm1234_8base, z_imm1234_0base),
	(z_tfr, z_reg, reg_xy, lea_reg_xys_opr, lea_reg_xys, rel_15_7),
	(decode_rel_15_7, cmp_xy, sub_d6_x_y, sub_d6_y_x),
	(ld_18bit_decode, mul_decode, bm_decode, bm_rel_decode),
	(mov_imm_opr, ld_18bit_decode, exg_sex_decode),
	(loop_primitive_decode, shift_decode, psh_pul_decode),
	(bit_field_decode): Similarly.
	(z_decode_signed_value, decode_signed_value): Similarly.  Add arg
	to return value, update callers.
	(x_opr_decode_with_size): Check all reads, returning NULL on fail.
	Don't segfault on NULL operand.
	(decode_operation): Return OP_INVALID on first fail.
	(decode_s12z): Check all reads, returning -1 on fail.

2020-03-20  Alan Modra  <amodra@gmail.com>

	* metag-dis.c (print_insn_metag): Don't ignore status from
	read_memory_func.

2020-03-20  Alan Modra  <amodra@gmail.com>

	* nds32-dis.c (print_insn_nds32): Remove unnecessary casts.
	Initialize parts of buffer not written when handling a possible
	2-byte insn at end of section.  Don't attempt decoding of such
	an insn by the 4-byte machinery.

2020-03-20  Alan Modra  <amodra@gmail.com>

	* ppc-dis.c (print_insn_powerpc): Only clear needed bytes of
	partially filled buffer.  Prevent lookup of 4-byte insns when
	only VLE 2-byte insns are possible due to section size.  Print
	".word" rather than ".long" for 2-byte leftovers.

2020-03-17  Sergey Belyashov  <sergey.belyashov@gmail.com>

	PR 25641
	* z80-dis.c: Fix disassembling ED+A4/AC/B4/BC opcodes.

2020-03-13  Jan Beulich  <jbeulich@suse.com>

	* i386-dis.c (X86_64_0D): Rename to ...
	(X86_64_0E): ... this.

2020-03-09  H.J. Lu  <hongjiu.lu@intel.com>

	* Makefile.am ($(srcdir)/i386-init.h): Also pass -P to $(CPP).
	* Makefile.in: Regenerated.

2020-03-09  Jan Beulich  <jbeulich@suse.com>

	* i386-opc.tbl (avx_irel): New. Use is for AVX512 vpcmp*
	3-operand pseudos.
	* i386-tbl.h: Re-generate.

2020-03-09  Jan Beulich  <jbeulich@suse.com>

	* i386-opc.tbl (xop_elem, xop_irel, xop_sign): New. Use them for XOP vpcom*,
	vprot*, vpsha*, and vpshl*.
	* i386-tbl.h: Re-generate.

2020-03-09  Jan Beulich  <jbeulich@suse.com>

	* i386-opc.tbl (avx_frel): New. Use it for AVX/AVX512 vcmpps,
	vcmpss, vcmppd, and vcmpsd 3-operand pseudo-ops.
	* i386-tbl.h: Re-generate.

2020-03-09  Jan Beulich  <jbeulich@suse.com>

	* i386-gen.c (set_bitfield): Ignore zero-length field names.
	* i386-opc.tbl (sse_frel): New. Use it for SSE/SSE2 cmpps,
	cmpss, cmppd, and cmpsd 2-operand pseudo-ops.
	* i386-tbl.h: Re-generate.

2020-03-09  Jan Beulich  <jbeulich@suse.com>

	* i386-gen.c (struct template_arg, struct template_instance,
	struct template_param, struct template, templates,
	parse_template, expand_templates): New.
	(process_i386_opcodes): Various local variables moved to
	expand_templates. Call parse_template and expand_templates.
	* i386-opc.tbl (cc): New. Use it for Jcc, SETcc, and CMOVcc.
	* i386-tbl.h: Re-generate.

2020-03-06  Jan Beulich  <jbeulich@suse.com>

	* i386-opc.tbl (vcvtdq2pd, vcvtps2pd, vcvtudq2pd, vcvtps2ph,
	vcvtps2qq, vcvtps2uqq, vcvttps2qq, vcvttps2uqq): Fold separate
	register and memory source templates. Replace VexW= by VexW*
	where applicable.
	* i386-tbl.h: Re-generate.

2020-03-06  Jan Beulich  <jbeulich@suse.com>

	* i386-opc.tbl: Drop IgnoreSize from various SIMD insns. Replace
	VexW= by VexW* and VexVVVV=1 by just VexVVVV where applicable.
	* i386-tbl.h: Re-generate.

2020-03-06  Jan Beulich  <jbeulich@suse.com>

	* i386-opc.tbl (fildll, fistpll, fisttpll): Add ATTSyntax.
	* i386-tbl.h: Re-generate.

2020-03-06  Jan Beulich  <jbeulich@suse.com>

	* i386-opc.tbl (movq): Drop NoRex64 from XMM/XMM SSE2AVX variants.
	(movmskps, pextrw, pinsrw, pmovmskb, movmskpd, extractps,
	pextrb, pinsrb, roundsd): Drop NoRex64 and where applicable use
	VexW0 on SSE2AVX variants.
	(vmovq): Drop NoRex64 from XMM/XMM variants.
	(vextractps, vmovmskpd, vmovmskps, vpextrb, vpextrw, vpinsrb,
	vpinsrw, vpmovmskb, vroundsd, vpmovmskb): Drop NoRex64 and where
	applicable use VexW0.
	* i386-tbl.h: Re-generate.

2020-03-06  Jan Beulich  <jbeulich@suse.com>

	* i386-gen.c (opcode_modifiers): Remove Rex64 field.
	* i386-opc.h (Rex64): Delete.
	(struct i386_opcode_modifier): Remove rex64 field.
	* i386-opc.tbl (crc32): Drop Rex64.
	Replace Rex64 with Size64 everywhere else.
	* i386-tbl.h: Re-generate.

2020-03-06  Jan Beulich  <jbeulich@suse.com>

	* i386-dis.c (OP_E_memory): Exclude recording of used address
	prefix for "bnd" modes only in 64-bit mode. Don't decode 16-bit
	addressed memory operands for MPX insns.

2020-03-06  Jan Beulich  <jbeulich@suse.com>

	* i386-opc.tbl (movmskps, mwait, vmread, vmwrite, invept,
	invvpid, invpcid, rdfsbase, rdgsbase, wrfsbase, wrgsbase, adcx,
	adox, mwaitx, rdpid, movdiri): Add IgnoreSize.
	(ptwrite): Split into non-64-bit and 64-bit forms.
	* i386-tbl.h: Re-generate.

2020-03-06  Jan Beulich  <jbeulich@suse.com>

	* i386-opc.tbl (tpause, umwait): Add IgnoreSize. Add 3-operand
	template.
	* i386-tbl.h: Re-generate.

2020-03-04  Jan Beulich  <jbeulich@suse.com>

	* i386-dis.c (PREFIX_0F01_REG_3_RM_1): New.
	(prefix_table): Move vmmcall here. Add vmgexit.
	(rm_table): Replace vmmcall entry by prefix_table[] escape.
	* i386-gen.c (cpu_flag_init): Add CPU_SEV_ES_FLAGS entry.
	(cpu_flags): Add CpuSEV_ES entry.
	* i386-opc.h (CpuSEV_ES): New.
	(union i386_cpu_flags): Add cpusev_es field.
	* i386-opc.tbl (vmgexit): New.
	* i386-init.h, i386-tbl.h: Re-generate.

2020-03-03  H.J. Lu  <hongjiu.lu@intel.com>

	* i386-gen.c (opcode_modifiers): Replace IgnoreSize/DefaultSize
	with MnemonicSize.
	* i386-opc.h (IGNORESIZE): New.
	(DEFAULTSIZE): Likewise.
	(IgnoreSize): Removed.
	(DefaultSize): Likewise.
	(MnemonicSize): New.
	(i386_opcode_modifier): Replace ignoresize/defaultsize with
	mnemonicsize.
	* i386-opc.tbl (IgnoreSize): New.
	(DefaultSize): Likewise.
	* i386-tbl.h: Regenerated.

2020-03-03  Sergey Belyashov  <sergey.belyashov@gmail.com>

	PR 25627
	* z80-dis.c: Fix disassembly of LD IY,(HL) and D (HL),IX
	instructions.

2020-03-03  H.J. Lu  <hongjiu.lu@intel.com>

	PR gas/25622
	* i386-opc.tbl: Add IgnoreSize to cvtsi2sd, cvtsi2ss, vcvtsi2sd,
	vcvtsi2ss, vcvtusi2sd and vcvtusi2ss for AT&T syntax.
	* i386-tbl.h: Regenerated.

2020-02-26  Alan Modra  <amodra@gmail.com>

	* aarch64-asm.c: Indent labels correctly.
	* aarch64-dis.c: Likewise.
	* aarch64-gen.c: Likewise.
	* aarch64-opc.c: Likewise.
	* alpha-dis.c: Likewise.
	* i386-dis.c: Likewise.
	* nds32-asm.c: Likewise.
	* nfp-dis.c: Likewise.
	* visium-dis.c: Likewise.

2020-02-25  Claudiu Zissulescu <claziss@gmail.com>

	* arc-regs.h (int_vector_base): Make it available for all ARC
	CPUs.

2020-02-20  Nelson Chu  <nelson.chu@sifive.com>

	* riscv-dis.c (print_insn_args): Updated since the DECLARE_CSR is
	changed.

2020-02-19  Nelson Chu  <nelson.chu@sifive.com>

	* riscv-opc.c (riscv_opcodes): Convert add/addi to the compressed
	c.mv/c.li if rs1 is zero.

2020-02-17  H.J. Lu  <hongjiu.lu@intel.com>

	* i386-gen.c (cpu_flag_init): Replace CpuABM with
	CpuLZCNT|CpuPOPCNT.  Add CpuPOPCNT to CPU_SSE4_2_FLAGS.  Add
	CPU_POPCNT_FLAGS.
	(cpu_flags): Remove CpuABM.  Add CpuPOPCNT.
	* i386-opc.h (CpuABM): Removed.
	(CpuPOPCNT): New.
	(i386_cpu_flags): Remove cpuabm.  Add cpupopcnt.
	* i386-opc.tbl: Replace CpuABM|CpuSSE4_2 with CpuPOPCNT on
	popcnt.  Remove CpuABM from lzcnt.
	* i386-init.h: Regenerated.
	* i386-tbl.h: Likewise.

2020-02-17  Jan Beulich  <jbeulich@suse.com>

	* i386-opc.tbl (vcvtsi2sd, vcvtsi2ss, vcvtusi2sd, vcvtusi2ss):
	Fold CpuNo64 and Cpu64 templates. Use VexLIG/EVexLIG and VexW0/
	VexW1 instead of open-coding them.
	* i386-tbl.h: Re-generate.

2020-02-17  Jan Beulich  <jbeulich@suse.com>

	* i386-opc.tbl (AddrPrefixOpReg): Define.
	(monitor, invlpga, vmload, vmrun, vmsave, clzero, monitorx,
	umonitor, movdir64b, enqcmd, enqcmds): Fold Cpu64 and CpuNo64
	templates. Drop NoRex64.
	* i386-tbl.h: Re-generate.

2020-02-17  Jan Beulich  <jbeulich@suse.com>

	PR gas/6518
	* i386-opc.tbl (vcvtpd2dq, vcvtpd2ps, vcvttpd2dq, vcvtpd2udq,
	vcvttpd2udq, vcvtqq2ps, vcvtuqq2ps): Split XMM/YMM source forms
	into Intel syntax instance (with Unpsecified) and AT&T one
	(without).
	(vcvtneps2bf16): Likewise, along with folding the two so far
	separate ones.
	* i386-tbl.h: Re-generate.

2020-02-16  H.J. Lu  <hongjiu.lu@intel.com>

	* i386-gen.c (cpu_flag_init): Remove CPU_ANY_SSE3_FLAGS from
	CPU_ANY_SSE4A_FLAGS.

2020-02-17  Alan Modra  <amodra@gmail.com>

	* i386-gen.c (cpu_flag_init): Correct last change.

2020-02-16  H.J. Lu  <hongjiu.lu@intel.com>

	* i386-gen.c (cpu_flag_init): Add CPU_ANY_SSE4A_FLAGS.  Remove
	CPU_ANY_SSE4_FLAGS.

2020-02-14  H.J. Lu  <hongjiu.lu@intel.com>

	* i386-opc.tbl (movsx): Remove Intel syntax comments.
	(movzx): Likewise.

2020-02-14  Jan Beulich  <jbeulich@suse.com>

	PR gas/25438
	* i386-opc.tbl (movsx): Fold patterns. Also allow Reg32 as
	destination for Cpu64-only variant.
	(movzx): Fold patterns.
	* i386-tbl.h: Re-generate.

2020-02-13  Jan Beulich  <jbeulich@suse.com>

	* i386-gen.c (cpu_flag_init): Move CpuSSE4a from
	CPU_ANY_SSE_FLAGS entry to CPU_ANY_SSE3_FLAGS one. Add
	CPU_ANY_SSE4_FLAGS entry.
	* i386-init.h: Re-generate.

2020-02-12  Jan Beulich  <jbeulich@suse.com>

	* i386-opc.tbl (vfpclasspd, vfpclassps): Add Intel sytax form
	with Unspecified, making the present one AT&T syntax only.
	* i386-tbl.h: Re-generate.

2020-02-12  Jan Beulich  <jbeulich@suse.com>

	* i386-opc.tbl (jmp): Fold CpuNo64 and Amd64 direct variants.
	* i386-tbl.h: Re-generate.

2020-02-12  Jan Beulich  <jbeulich@suse.com>

	PR gas/24546
	* i386-dis.c (putop): Handle REX.W in '^' case for Intel64 mode.
	* i386-opc.tbl (lfs, lgs, lss, lcall, ljmp): Split into
	Amd64 and Intel64 templates.
	(call, jmp): Likewise for far indirect variants. Dro
	Unspecified.
	* i386-tbl.h: Re-generate.

2020-02-11  Jan Beulich  <jbeulich@suse.com>

	* i386-gen.c (opcode_modifiers): Remove ShortForm entry.
	* i386-opc.h (ShortForm): Delete.
	(struct i386_opcode_modifier): Remove shortform field.
	* i386-opc.tbl (mov, movabs, push, pop, xchg, inc, dec, fld,
	fst, fstp, fxch, fcom, fcomp, fucom, fucomp, fadd, faddp, fsub,
	fsubp, fsubr, fsubrp, fmul, fmulp, fdiv, fdivp, fdivr, fdivrp,
	ffreep, bswap, fcmov*, fcomi, fcomip, fucomi, fucomip, movq):
	Drop ShortForm.
	* i386-tbl.h: Re-generate.

2020-02-11  Jan Beulich  <jbeulich@suse.com>

	* i386-opc.tbl (fcomi, fucomi, fcomip, fcompi, fucomip,
	fucompi): Drop ShortForm from operand-less templates.
	* i386-tbl.h: Re-generate.

2020-02-11  Alan Modra  <amodra@gmail.com>

	* cgen-ibld.in (extract_normal): Set *valuep on all return paths.
	* bpf-ibld.c, * epiphany-ibld.c, * fr30-ibld.c, * frv-ibld.c,
	* ip2k-ibld.c, * iq2000-ibld.c, * lm32-ibld.c, * m32c-ibld.c,
	* m32r-ibld.c, * mep-ibld.c, * mt-ibld.c, * or1k-ibld.c,
	* xc16x-ibld.c, * xstormy16-ibld.c: Regenerate.

2020-02-10  Matthew Malcomson  <matthew.malcomson@arm.com>

	* arm-dis.c (print_insn_cde): Define 'V' parse character.
	(cde_opcodes): Add VCX* instructions.

2020-02-10  Stam Markianos-Wright  <stam.markianos-wright@arm.com>
	    Matthew Malcomson  <matthew.malcomson@arm.com>

	* arm-dis.c (struct cdeopcode32): New.
	(CDE_OPCODE): New macro.
	(cde_opcodes): New disassembly table.
	(regnames): New option to table.
	(cde_coprocs): New global variable.
	(print_insn_cde): New
	(print_insn_thumb32): Use print_insn_cde.
	(parse_arm_disassembler_options): Parse coprocN args.

2020-02-10  H.J. Lu  <hongjiu.lu@intel.com>

	PR gas/25516
	* i386-gen.c (opcode_modifiers): Replace AMD64 and Intel64
	with ISA64.
	* i386-opc.h (AMD64): Removed.
	(Intel64): Likewose.
	(AMD64): New.
	(INTEL64): Likewise.
	(INTEL64ONLY): Likewise.
	(i386_opcode_modifier): Replace amd64 and intel64 with isa64.
	* i386-opc.tbl (Amd64): New.
	(Intel64): Likewise.
	(Intel64Only): Likewise.
	Replace AMD64 with Amd64.  Update sysenter/sysenter with
	Cpu64 and Intel64Only.  Remove AMD64 from sysenter/sysenter.
	* i386-tbl.h: Regenerated.

2020-02-07  Sergey Belyashov  <sergey.belyashov@gmail.com>

	PR 25469
	* z80-dis.c: Add support for GBZ80 opcodes.

2020-02-04  Alan Modra  <amodra@gmail.com>

	* d30v-dis.c (print_insn): Make "val" and "opnum" unsigned.

2020-02-03  Alan Modra  <amodra@gmail.com>

	* m32c-ibld.c: Regenerate.

2020-02-01  Alan Modra  <amodra@gmail.com>

	* frv-ibld.c: Regenerate.

2020-01-31  Jan Beulich  <jbeulich@suse.com>

	* i386-dis.c (EXxmm_mdq, xmm_mdq_mode): Delete.
	(intel_operand_size, OP_EX): Drop xmm_mdq_mode case label.
	(OP_E_memory): Replace xmm_mdq_mode case label by
	vex_scalar_w_dq_mode one.
	* i386-dis-evex-prefix.h: Replace EXxmm_mdq by EXVexWdqScalar.

2020-01-31  Jan Beulich  <jbeulich@suse.com>

	* i386-dis.c (EXVexWdq, vex_w_dq_mode): Delete.
	(vex_vsib_d_w_dq_mode, vex_vsib_q_w_dq_mode,
	vex_scalar_w_dq_mode): Don't refer to vex_w_dq_mode in comments.
	(intel_operand_size): Drop vex_w_dq_mode case label.

2020-01-31  Richard Sandiford  <richard.sandiford@arm.com>

	* aarch64-tbl.h (aarch64_opcode): Set C_MAX_ELEM for SVE bfcvt.
	Remove C_SCAN_MOVPRFX for SVE bfcvtnt.

2020-01-30  Alan Modra  <amodra@gmail.com>

	* m32c-ibld.c: Regenerate.

2020-01-30  Jose E. Marchesi  <jose.marchesi@oracle.com>

	* bpf-opc.c: Regenerate.

2020-01-30  Jan Beulich  <jbeulich@suse.com>

	* i386-dis.c (X86_64_C2, X86_64_C3): New enumerators.
	(dis386): Use them to replace C2/C3 table entries.
	(x86_64_table): Add X86_64_C2 and X86_64_C3 entries.
	* i386-opc.tbl (ret): Split Cpu64 entries into AMD64 and Intel64
	ones. Use Size64 instead of DefaultSize on Intel64 ones.
	* i386-tbl.h: Re-generate.

2020-01-30  Jan Beulich  <jbeulich@suse.com>

	* i386-opc.tbl (call): Drop DefaultSize from Intel64 JumpDword
	forms.
	(fldenv, fnstenv, fstenv, fnsave, fsave, frstor): Drop
	DefaultSize.
	* i386-tbl.h: Re-generate.

2020-01-30  Alan Modra  <amodra@gmail.com>

	* tic4x-dis.c (tic4x_dp): Make unsigned.

2020-01-27  H.J. Lu  <hongjiu.lu@intel.com>
	    Jan Beulich  <jbeulich@suse.com>

	PR binutils/25445
	* i386-dis.c (MOVSXD_Fixup): New function.
	(movsxd_mode): New enum.
	(x86_64_table): Use MOVSXD_Fixup and movsxd_mode on movsxd.
	(intel_operand_size): Handle movsxd_mode.
	(OP_E_register): Likewise.
	(OP_G): Likewise.
	* i386-opc.tbl: Remove Rex64 and allow 32-bit destination
	register on movsxd.  Add movsxd with 16-bit destination register
	for AMD64 and Intel64 ISAs.
	* i386-tbl.h: Regenerated.

2020-01-27  Tamar Christina  <tamar.christina@arm.com>

	PR 25403
	* aarch64-tbl.h (struct aarch64_opcode): Re-order cfinv.
	* aarch64-asm-2.c: Regenerate
	* aarch64-dis-2.c: Likewise.
	* aarch64-opc-2.c: Likewise.

2020-01-21  Jan Beulich  <jbeulich@suse.com>

	* i386-opc.tbl (sysret): Drop DefaultSize.
	* i386-tbl.h: Re-generate.

2020-01-21  Jan Beulich  <jbeulich@suse.com>

	* i386-opc.tbl (vcvtneps2bf16x): Add Broadcast, Xmmword, and
	Dword.
	(vcvtneps2bf16y): Add Broadcast, Ymmword, and Dword.
	* i386-tbl.h: Re-generate.

2020-01-20  Nick Clifton  <nickc@redhat.com>

	* po/de.po: Updated German translation.
	* po/pt_BR.po: Updated Brazilian Portuguese translation.
	* po/uk.po: Updated Ukranian translation.

2020-01-20  Alan Modra  <amodra@gmail.com>

	* hppa-dis.c (fput_const): Remove useless cast.

2020-01-20  Alan Modra  <amodra@gmail.com>

	* arm-dis.c (print_insn_arm): Wrap 'T' value.

2020-01-18  Nick Clifton  <nickc@redhat.com>

	* configure: Regenerate.
	* po/opcodes.pot: Regenerate.

2020-01-18  Nick Clifton  <nickc@redhat.com>

	Binutils 2.34 branch created.

2020-01-17  Christian Biesinger  <cbiesinger@google.com>

	* opintl.h: Fix spelling error (seperate).

2020-01-17  H.J. Lu  <hongjiu.lu@intel.com>

	* i386-opc.tbl: Add {vex} pseudo prefix.
	* i386-tbl.h: Regenerated.

2020-01-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>

	PR 25376
	* opcodes/arm-dis.c (coprocessor_opcodes): Use CORE_HIGH for MVE bits.
	(neon_opcodes): Likewise.
	(select_arm_features): Make sure we enable MVE bits when selecting
	armv8.1-m.main.  Make sure we do not enable MVE bits when not selecting
	any architecture.

2020-01-16  Jan Beulich  <jbeulich@suse.com>

	* i386-opc.tbl: Drop stale comment from XOP section.

2020-01-16  Jan Beulich  <jbeulich@suse.com>

	* i386-opc.tbl (movq): Add VexWIG to SSE2AVX XMM->XMM forms.
	(extractps): Add VexWIG to SSE2AVX forms.
	* i386-tbl.h: Re-generate.

2020-01-16  Jan Beulich  <jbeulich@suse.com>

	* i386-opc.tbl (pextrq, pinsrq): Drop IgnoreSize and Qword. Drop
	Size64 from and use VexW1 on SSE2AVX forms.
	(vpextrq, vpinsrq): Drop IgnoreSize and Qword. Drop Size64 from
	VEX-encoded forms. Add Cpu64 to EVEX-encoded forms. Use VexW1.
	* i386-tbl.h: Re-generate.

2020-01-15  Alan Modra  <amodra@gmail.com>

	* tic4x-dis.c (tic4x_version): Make unsigned long.
	(optab, optab_special, registernames): New file scope vars.
	(tic4x_print_register): Set up registernames rather than
	malloc'd registertable.
	(tic4x_disassemble): Delete optable and optable_special.  Use
	optab and optab_special instead.  Throw away old optab,
	optab_special and registernames when info->mach changes.

2020-01-14  Sergey Belyashov  <sergey.belyashov@gmail.com>

	PR 25377
	* z80-dis.c (suffix): Use .db instruction to generate double
	prefix.

2020-01-14  Alan Modra  <amodra@gmail.com>

	* z8k-dis.c (unpack_instr): Formatting.  Cast unsigned short
	values to unsigned before shifting.

2020-01-13  Thomas Troeger  <tstroege@gmx.de>

	* arm-dis.c (print_insn_arm): Fill in insn info fields for control
	flow instructions.
	(print_insn_thumb16, print_insn_thumb32): Likewise.
	(print_insn): Initialize the insn info.
	* i386-dis.c (print_insn): Initialize the insn info fields, and
	detect jumps.

2012-01-13  Claudiu Zissulescu <claziss@gmail.com>

	* arc-opc.c (C_NE): Make it required.

2012-01-13  Claudiu Zissulescu <claziss@gmail.com>

        * opcode/arc-dis.c (regnames): Correct ACCL/ACCH naming, fix typo
	reserved register name.

2020-01-13  Alan Modra  <amodra@gmail.com>

	* ns32k-dis.c (Is_gen): Use strchr, add 'f'.
	(print_insn_ns32k): Adjust ioffset for 'f' index_offset.

2020-01-13  Alan Modra  <amodra@gmail.com>

	* wasm32-dis.c (print_insn_wasm32): Localise variables.  Store
	result of wasm_read_leb128 in a uint64_t and check that bits
	are not lost when copying to other locals.  Use uint32_t for
	most locals.  Use PRId64 when printing int64_t.

2020-01-13  Alan Modra  <amodra@gmail.com>

	* score-dis.c: Formatting.
	* score7-dis.c: Formatting.

2020-01-13  Alan Modra  <amodra@gmail.com>

	* score-dis.c (print_insn_score48): Use unsigned variables for
	unsigned values.  Don't left shift negative values.
	(print_insn_score32): Likewise.
	* score7-dis.c (print_insn_score32, print_insn_score16): Likewise.

2020-01-13  Alan Modra  <amodra@gmail.com>

	* tic4x-dis.c (tic4x_print_register): Remove dead code.

2020-01-13  Alan Modra  <amodra@gmail.com>

	* fr30-ibld.c: Regenerate.

2020-01-13  Alan Modra  <amodra@gmail.com>

	* xgate-dis.c (print_insn): Don't left shift signed value.
	(ripBits): Formatting, use 1u.

2020-01-10  Alan Modra  <amodra@gmail.com>

	* tilepro-opc.c (parse_insn_tilepro): Make opval unsigned.
	* tilegx-opc.c (parse_insn_tilegx): Likewise.  Delete raw_opval.

2020-01-10  Alan Modra  <amodra@gmail.com>

	* m10300-dis.c (disassemble): Move extraction of DREG, AREG, RREG,
	and XRREG value earlier to avoid a shift with negative exponent.
	* m10200-dis.c (disassemble): Similarly.

2020-01-09  Nick Clifton  <nickc@redhat.com>

	PR 25224
	* z80-dis.c (ld_ii_ii): Use correct cast.

2020-01-03  Sergey Belyashov  <sergey.belyashov@gmail.com>

	PR 25224
	* z80-dis.c (ld_ii_ii): Use character constant when checking
	opcode byte value.

2020-01-09  Jan Beulich  <jbeulich@suse.com>

	* i386-dis.c (SEP_Fixup): New.
	(SEP): Define.
	(dis386_twobyte): Use it for sysenter/sysexit.
	(enum x86_64_isa): Change amd64 enumerator to value 1.
	(OP_J): Compare isa64 against intel64 instead of amd64.
	* i386-opc.tbl (sysenter, sysexit): Split into AMD64 and Intel64
	forms.
	* i386-tbl.h: Re-generate.

2020-01-08  Alan Modra  <amodra@gmail.com>

	* z8k-dis.c: Include libiberty.h
	(instr_data_s): Make max_fetched unsigned.
	(z8k_lookup_instr): Make nibl_index and tabl_index unsigned.
	Don't exceed byte_info bounds.
	(output_instr): Make num_bytes unsigned.
	(unpack_instr): Likewise for nibl_count and loop.
	* z8kgen.c (gas <opcode_entry_type>): Make noperands, length and
	idx unsigned.
	* z8k-opc.h: Regenerate.

2020-01-07  Shahab Vahedi  <shahab@synopsys.com>

	* arc-tbl.h (llock): Use 'LLOCK' as class.
	(llockd): Likewise.
	(scond): Use 'SCOND' as class.
	(scondd): Likewise.
	(llockd): Set data_size_mode to 'C_ZZ_D' which is 64-bit.
	(scondd): Likewise.

2020-01-06  Alan Modra  <amodra@gmail.com>

	* m32c-ibld.c: Regenerate.

2020-01-06  Alan Modra  <amodra@gmail.com>

	PR 25344
	* z80-dis.c (suffix): Don't use a local struct buffer copy.
	Peek at next byte to prevent recursion on repeated prefix bytes.
	Ensure uninitialised "mybuf" is not accessed.
	(print_insn_z80): Don't zero n_fetch and n_used here,..
	(print_insn_z80_buf): ..do it here instead.

2020-01-04  Alan Modra  <amodra@gmail.com>

	* m32r-ibld.c: Regenerate.

2020-01-04  Alan Modra  <amodra@gmail.com>

	* cr16-dis.c (cr16_match_opcode): Avoid shift left of signed value.

2020-01-04  Alan Modra  <amodra@gmail.com>

	* crx-dis.c (match_opcode): Avoid shift left of signed value.

2020-01-04  Alan Modra  <amodra@gmail.com>

	* d30v-dis.c (print_insn): Avoid signed overflow in left shift.

2020-01-03  Jan Beulich  <jbeulich@suse.com>

	* aarch64-tbl.h (aarch64_opcode_table): Use
	SVE_ADDR_RX_LSL{1,2,3} for LD1RO{H,W,D}.

2020-01-03  Jan Beulich  <jbeulich@suse.com>

	* aarch64-tbl.h (aarch64_opcode_table): Correct SIMD
	forms of SUDOT and USDOT.

2020-01-03  Jan Beulich  <jbeulich@suse.com>

	* aarch64-tbl.h (aarch64_opcode_table): Drop 'i' from
	uzip{1,2}.
	* opcodes/aarch64-dis-2.c: Re-generate.

2020-01-03  Jan Beulich  <jbeulich@suse.com>

	* aarch64-tbl.h (aarch64_opcode_table): Correct 64-bit
	FMMLA encoding.
	* opcodes/aarch64-dis-2.c: Re-generate.

2020-01-02  Sergey Belyashov  <sergey.belyashov@gmail.com>

	* z80-dis.c: Add support for eZ80 and Z80 instructions.

2020-01-01  Alan Modra  <amodra@gmail.com>

	Update year range in copyright notice of all files.

For older changes see ChangeLog-2019

Copyright (C) 2020 Free Software Foundation, Inc.

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