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* sim: Use host not target byte order for merging and splitting valuesAndrew Burgess2019-04-132-5/+14
* sim: fix all sim buildsAndrew Burgess2019-03-283-0/+8
* sim: fix aarch64 sim buildAndrew Burgess2019-03-283-0/+7
* sim/common: Fix warnings: "warning: implicit declaration of function..."Stafford Horne2019-03-287-0/+28
* sim/common: convert sim-arange to use sim-inlineStafford Horne2019-03-288-36/+83
* (gdb/sim) Move Mike Frysinger to past maintainers sectionJoel Brobecker2019-02-282-1/+5
* Add Andrew Burgess as global maintainer of gdb/ and sim/Simon Marchi2019-02-132-1/+6
* Fix the sim buildTom Tromey2019-01-265-4/+51
* Actually remove definitions of DEFINE_NON_INLINE_P and DEFINE_INLINE_PSimon Marchi2019-01-162-4/+1
* Do not expand macros to 'defined'Pavel I. Kryukov2019-01-162-5/+7
* sim: Fix definition of SIM_ARANGE_INLINESimon Marchi2019-01-152-1/+5
* Add 'extern C' if simulator is written in C++Павел Крюков2019-01-032-0/+12
* Update copyright year range in all GDB files.Joel Brobecker2019-01-01618-618/+618
* sim: Don't overwrite stored errno in sim_syscall_multiAndrew Burgess2018-12-182-5/+5
* sim/cris: Fix references to cgen cpu directoryAndrew Burgess2018-12-062-10/+13
* sim/opcodes: Allow use of out of tree cgen source directoryAndrew Burgess2018-12-069-40/+100
* [src/erc32] Use ncurses instead of termcap on Cygwin tooJoel Sherrill2018-10-303-10/+15
* or1k: Add the l.muld, l.muldu, l.macu, l.msbu insnsRichard Henderson2018-10-0512-233/+1058
* Change "xor" name in cpu_core to allow building with iso646.h or C++ compilerКомпан, Вячеслав Олегович2018-09-283-4/+14
* Update my e-mail address, limit maintenance to MIPS I-IV ISAsMaciej W. Rozycki2018-07-212-1/+6
* Remove myself from target-specific MAINTAINERSDJ Delorie2018-07-192-4/+8
* sim: Add Stafford Horne as or1k maintainer.Stafford Horne2018-07-142-0/+5
* Bump to autoconf 2.69 and automake 1.15.1Simon Marchi2018-06-19132-17835/+19994
* config: Sync with GCCSimon Marchi2018-06-1832-974/+1037
* PR22069, Several instances of register accidentally spelled as regsiterAlan Modra2018-05-093-2/+7
* MAINTAINERS: Update my company e-mail addressMaciej W. Rozycki2018-01-222-1/+5
* Fix compile time warning (in the ARM simulator) about a print statement with ...Nick Clifton2018-01-022-1/+7
* Update copyright year range in all GDB filesJoel Brobecker2018-01-02618-618/+618
* sim: testsuite: add testsuite for or1k simPeter Gavin2017-12-1228-0/+6510
* sim: or1k: add autoconf generated filesStafford Horne2017-12-125-0/+16427
* sim: or1k: add cgen generated filesStafford Horne2017-12-1211-0/+27536
* sim: or1k: add or1k target to simStafford Horne2017-12-1211-0/+1637
* sim: cgen: add MUL2OFSI and MUL1OFSI functions (needed for OR1K l.mul[u])Peter Gavin2017-12-122-0/+25
* sim: cgen: add remainder functions (needed for OR1K lf.rem.[sd])Peter Gavin2017-12-125-5/+149
* FT32: support for FT32B processor - part 2/2James Bowman2017-11-012-7/+19
* FT32: support for FT32B processor - part 1James Bowman2017-10-122-7/+15
* Add myself as ft32 maintainer for sim.James Bowman2017-10-122-0/+5
* Update my email address.Jim Wilson2017-10-032-1/+5
* [SIM, ARM] Fix build failureYao Qi2017-09-212-1/+8
* Honor an existing CC_FOR_BUILD in the environment for sim.John Baldwin2017-09-0659-202/+434
* Define an error function in the PPC simulator library.John Baldwin2017-09-042-0/+15
* Fix simulatorAnthony Green2017-09-042-7/+16
* Fix simulation of MSP430's open system call.Jozef Lawrynowicz2017-08-292-10/+30
* Correct check for endiannessMichael Eager2017-06-022-1/+5
* Refactor disassembler selectionYao Qi2017-05-242-1/+9
* Fix ldn/stn multiple instructions. Fix testcases with unaligned data.Jim Wilson2017-04-2214-202/+454
* Add support for fcvtl and fcvtl2.Jim Wilson2017-04-084-0/+112
* Support the fcmXX zero instructions.Jim Wilson2017-04-084-0/+232
* Fix bug with cmn/adds where C flag was incorrectly set.Jim Wilson2017-03-254-1/+27
* Fix umulh and smulh bugs. Fix bugs in last week's sumov.s testsuite.Jim Wilson2017-03-035-9/+89
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