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* sim: v850: reduce extra header inclusion to igen filesMike Frysinger2023-01-181-0/+4
* sim: v850: drop redundant defineMike Frysinger2023-01-181-4/+0
* sim: formally assume unistd.h always exists (via gnulib)Mike Frysinger2023-01-161-2/+0
* sim: modules.c: fix generation after recent refactorsMike Frysinger2023-01-151-0/+3
* sim: common: move modules.c to source trackingMike Frysinger2023-01-141-1/+2
* sim: build: drop most recursive build depsMike Frysinger2023-01-141-2/+1
* sim: common: move libcommon.a objects to sourcesMike Frysinger2023-01-141-2/+2
* sim: build: drop subdir Makefile.in filesMike Frysinger2023-01-111-22/+0
* sim: move arch-specific file compilation of common/ files to top-levelMike Frysinger2023-01-101-2/+2
* sim: v850: move arch-specific file compilation to top-levelMike Frysinger2023-01-101-3/+2
* sim: build: drop support for creating libsim.a in subdirsMike Frysinger2023-01-101-2/+0
* sim: v850: move libsim.a creation to top-levelMike Frysinger2023-01-102-5/+27
* sim: modules: trigger generation from top-levelMike Frysinger2023-01-101-0/+1
* sim: build: move generated headers to built sourcesMike Frysinger2023-01-021-0/+9
* Update copyright year range in header of all files managed by GDBJoel Brobecker2023-01-012-2/+2
* sim: cpu: change default init to handle all cpusMike Frysinger2022-12-251-1/+1
* sim: v850: fix SMP compileMike Frysinger2022-12-253-81/+84
* sim: igen: drop move-if-changed usageMike Frysinger2022-12-241-30/+15
* sim: v850: standardize the arch-specific settings a littleMike Frysinger2022-12-236-725/+733
* sim: move bfd.h include out of sim-main.hMike Frysinger2022-12-221-2/+0
* sim: v850: switch from SIM_ADDR to address_wordMike Frysinger2022-12-222-4/+4
* sim: enable common sim_cpu usage everywhereMike Frysinger2022-12-211-2/+0
* sim: v850: invert sim_cpu storageMike Frysinger2022-12-213-20/+23
* sim: v850: rename v850.dc to align with other portsMike Frysinger2022-11-112-1/+1
* sim: v850: drop subdir configure logicMike Frysinger2022-11-074-2955/+2
* sim: run: move linking into top-levelMike Frysinger2022-11-051-0/+8
* sim: build: remove various obsolete generation dep variablesMike Frysinger2022-11-041-4/+0
* sim: v850: switch to standard (high-level) trace definesMike Frysinger2022-11-033-6/+2
* sim: common: change sim_{fetch,store}_register helpers to use void* buffersMike Frysinger2022-11-021-4/+4
* sim: reg: constify store helperMike Frysinger2022-10-311-2/+2
* sim: common: change sim_read & sim_write to use void* buffersMike Frysinger2022-10-311-3/+3
* Fix for v850e divq instructionJeff Law2022-04-061-2/+2
* Fix "bins" simulation for v850e3v5Jeff Law2022-04-061-1/+8
* Fix for MUL instruction on the v850Jeff Law2022-03-291-2/+2
* sim: gdbinit: hoist setup to common codeMike Frysinger2022-02-211-9/+0
* sim: v850: migrate to standard uintXX_t typesMike Frysinger2022-01-065-111/+105
* Automatic Copyright Year update after running gdb/copyright.pyJoel Brobecker2022-01-012-2/+2
* sim: use ## for automake commentsMike Frysinger2021-12-091-18/+18
* sim: v850: switch to new target-newlib-syscallMike Frysinger2021-11-283-67/+26
* sim: split program path out of argv vectorMike Frysinger2021-11-151-5/+1
* sim: hoist mn10300 & v850 igen rules up to common buildsMike Frysinger2021-11-022-67/+87
* sim: v850: delete old gencode logicMike Frysinger2021-10-311-7/+2
* sim: igen: tighten up build outputMike Frysinger2021-10-311-1/+1
* sim: silence stamp touch rulesMike Frysinger2021-10-311-1/+1
* sim: standardize move-if-change rulesMike Frysinger2021-10-311-15/+15
* sim: mips/v850: remove redundant variable setupMike Frysinger2021-10-311-2/+0
* sim: rename ChangeLog files to ChangeLog-2021Mike Frysinger2021-08-171-0/+0
* sim: unify reserved instruction bits settingsMike Frysinger2021-07-014-24/+6
* sim: unify scache settingsMike Frysinger2021-06-301-2/+0
* sim: move default model to the runtime sim stateMike Frysinger2021-06-302-2/+4
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