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* sim: fully merge sim_state_base into sim_stateMike Frysinger2021-05-172-2/+4
* sim: riscv: invert sim_state storageMike Frysinger2021-05-174-12/+22
* sim: switch config.h usage to defs.hMike Frysinger2021-05-164-3/+10
* sim: riscv: move __int128 check to configureMike Frysinger2021-05-164-3/+21
* sim: clean up explicit environment build callsMike Frysinger2021-05-123-23/+5
* sim: add support for build-time ar & ranlibMike Frysinger2021-05-042-2/+14
* sim: nrun: add local strsignal prototypeMike Frysinger2021-05-013-2/+12
* sim: riscv: fix building on 32-bit hosts w/out int128Mike Frysinger2021-05-012-1/+5
* sim: riscv: switch MIN/MAX to common min/maxMike Frysinger2021-04-262-7/+9
* sim: enable hardware support by defaultMike Frysinger2021-04-264-5/+120
* Do not check for sys/time.h or sys/times.hTom Tromey2021-04-223-14/+6
* Require GNU makeTom Tromey2021-04-222-67/+6
* sim: regen against sim/m4/Mike Frysinger2021-04-212-11/+15
* sim: use -Werror when probing for supported warning flagsSimon Marchi2021-04-212-1/+5
* sim: switch to AC_CHECK_HEADERS_ONCEMike Frysinger2021-04-181-52/+47
* sim: switch to AC_CHECK_FUNCS_ONCE & merge a littleMike Frysinger2021-04-182-25/+52
* sim: cgen: move cgen_cpu_max_extra_bytes logic into the common codeMike Frysinger2021-04-122-1/+5
* sim: unify toolchain settingsMike Frysinger2021-04-023-153/+162
* sim: set up build-time compiler settingsMike Frysinger2021-02-281-9/+10
* sim: use AC_CHECK_TOOL to find arMike Frysinger2021-02-281-3/+93
* sim: require AC_PROG_CPP explicitlyMike Frysinger2021-02-282-140/+145
* sim: common: split up acinclude.m4 into individual m4 filesMike Frysinger2021-02-214-10/+35
* RISC-V: PR27158, fixed UJ/SB types and added CSS/CL/CS types for .insn.Nelson Chu2021-02-191-3/+3
* sim: switch to AC_CONFIG_MACRO_DIRSMike Frysinger2021-02-134-1834/+35
* sim: common: switch AC_CONFIG_HEADERSMike Frysinger2021-02-061-3/+2
* sim: drop use of bfd/configure.hostMike Frysinger2021-02-062-6/+6
* gdb: riscv: enable sim integrationMike Frysinger2021-02-042-0/+76
* sim: riscv: new portMike Frysinger2021-02-0412-0/+18137
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