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* sim: riscv: add missing AC_MSG_RESULT callMike Frysinger2022-11-071-0/+1
* sim: riscv: drop subdir configure logicMike Frysinger2022-11-075-3129/+23
* sim: run: move linking into top-levelMike Frysinger2022-11-051-0/+25
* sim: common: change sim_{fetch,store}_register helpers to use void* buffersMike Frysinger2022-11-021-2/+2
* sim: reg: constify store helperMike Frysinger2022-10-311-1/+1
* sim: common: change sim_read & sim_write to use void* buffersMike Frysinger2022-10-311-5/+5
* sim: mips/ppc/riscv: re-add AC_CANONICAL_SYSTEM [PR sim/29439]Mike Frysinger2022-10-232-0/+162
* sim/riscv: fix multiply instructions on simulatorTsukasa OI2022-10-111-0/+1
* sim/riscv: Complete tidying up with SBREAKTsukasa OI2022-09-051-3/+3
* sim: gdbinit: hoist setup to common codeMike Frysinger2022-02-211-9/+0
* sim: riscv: migrate to standard uintXX_t typesMike Frysinger2022-01-061-28/+28
* Automatic Copyright Year update after running gdb/copyright.pyJoel Brobecker2022-01-016-6/+6
* sim: riscv: switch to new target-newlib-syscallMike Frysinger2021-11-282-3/+2
* sim: callback: expose argv & environMike Frysinger2021-11-161-0/+5
* sim: keep track of program environment stringsMike Frysinger2021-11-161-0/+6
* sim: split program path out of argv vectorMike Frysinger2021-11-151-4/+1
* sim: drop unused targ-vals.h includesMike Frysinger2021-10-311-2/+0
* sim: rename ChangeLog files to ChangeLog-2021Mike Frysinger2021-08-171-0/+0
* sim: unify reserved instruction bits settingsMike Frysinger2021-07-012-2/+4
* sim: unify scache settingsMike Frysinger2021-06-302-2/+4
* sim: move default model to the runtime sim stateMike Frysinger2021-06-305-37/+8
* sim: namespace sim_machsMike Frysinger2021-06-303-1/+11
* sim: model: constify sim_machs storageMike Frysinger2021-06-292-1/+5
* sim: drop configure scripts for simple portsMike Frysinger2021-06-222-0/+11
* sim: unify hardware settingsMike Frysinger2021-06-213-49/+5
* sim: hw: rework configure option & device selectionMike Frysinger2021-06-212-37/+29
* sim: delete SIM_AC_COMMON macroMike Frysinger2021-06-204-5/+5
* sim: unify general maintainer settingsMike Frysinger2021-06-202-124/+0
* sim: move sim-inline to the common codeMike Frysinger2021-06-203-36/+5
* sim: unify gettext/intl probing logicMike Frysinger2021-06-192-85/+0
* sim: unify toolchain dependency logicMike Frysinger2021-06-192-1109/+1
* sim: unify toolchain probing logicMike Frysinger2021-06-192-1360/+26
* sim: unify bfd library dependency testing logicMike Frysinger2021-06-193-7691/+6
* sim: unify various library testing logicMike Frysinger2021-06-192-141/+6
* sim: unify -Werror build settingsMike Frysinger2021-06-183-112/+6
* sim: move -Werror disabling to MakefileMike Frysinger2021-06-182-5/+8
* sim: split sim-signal.h include outMike Frysinger2021-06-182-0/+5
* sim: overhaul & unify endian settings managementMike Frysinger2021-06-175-58/+11
* sim: drop obsolete AC_EXEEXT callMike Frysinger2021-06-162-2/+4
* sim: drop arch-specific config.hMike Frysinger2021-06-163-280/+47
* sim: move dv-sockser define to CPPFLAGSMike Frysinger2021-06-153-8/+5
* sim: drop redundant SIM_AC_OPTION_WARNINGSMike Frysinger2021-06-143-96/+100
* sim: overhaul alignment settings managementMike Frysinger2021-06-124-56/+8
* sim: unify bug & package settingsMike Frysinger2021-06-123-87/+2
* sim: unify debug/stdio/trace/profile build settingsMike Frysinger2021-06-122-150/+2
* sim: unify environment build settingsMike Frysinger2021-06-123-32/+2
* sim: unify assert build settingsMike Frysinger2021-06-124-28/+6
* sim: unify platform function & header testsMike Frysinger2021-06-123-552/+6
* sim: fully merge sim_state_base into sim_stateMike Frysinger2021-05-172-2/+4
* sim: riscv: invert sim_state storageMike Frysinger2021-05-174-12/+22
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