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path: root/sim/pru/interp.c
Commit message (Expand)AuthorAgeFilesLines
* Update copyright year range in header of all files managed by GDBJoel Brobecker2023-01-011-1/+1
* sim: cpu: change default init to handle all cpusMike Frysinger2022-12-251-1/+1
* sim: use bfd_vma when reading start addr from bfd infoMike Frysinger2022-12-221-1/+1
* sim: pru: invert sim_cpu storageMike Frysinger2022-12-211-3/+27
* sim: common: change sim_{fetch,store}_register helpers to use void* buffersMike Frysinger2022-11-021-2/+2
* sim: reg: constify store helperMike Frysinger2022-10-311-1/+1
* sim: constify various integer readersMike Frysinger2022-10-311-4/+4
* Automatic Copyright Year update after running gdb/copyright.pyJoel Brobecker2022-01-011-1/+1
* sim: callback: expose argv & environMike Frysinger2021-11-161-0/+4
* sim: keep track of program environment stringsMike Frysinger2021-11-161-0/+6
* sim: split program path out of argv vectorMike Frysinger2021-11-151-4/+1
* sim: split sim-signal.h include outMike Frysinger2021-06-181-0/+1
* sim: overhaul & unify endian settings managementMike Frysinger2021-06-171-0/+1
* sim: overhaul alignment settings managementMike Frysinger2021-06-121-0/+3
* sim: switch config.h usage to defs.hMike Frysinger2021-05-161-1/+3
* sim: create header namespaceMike Frysinger2021-05-141-2/+2
* sim: cgen: move cgen_cpu_max_extra_bytes logic into the common codeMike Frysinger2021-04-121-1/+1
* Update copyright year range in all GDB filesJoel Brobecker2021-01-011-1/+1
* Update copyright year range in all GDB files.Joel Brobecker2020-01-011-1/+1
* sim: Add PRU simulator portDimitar Dimitrov2019-09-231-0/+848