summaryrefslogtreecommitdiff
path: root/sim/d10v/interp.c
Commit message (Expand)AuthorAgeFilesLines
* sim: sim_{create_inferior,open,parse_args}: constify argv/env slightlyMike Frysinger2016-01-061-2/+4
* sim: parse_args: display getopt error ourselvesMike Frysinger2016-01-031-3/+1
* sim: arm/d10v/h8300/m68hc11/microblaze/mips/mn10300/moxie/sh/v850: convert to...Mike Frysinger2015-12-301-6/+11
* sim: cr16/d10v: drop redundant call to sim_create_inferiorMike Frysinger2015-11-151-1/+0
* sim: d10v: drop global callback stateMike Frysinger2015-11-151-63/+59
* sim: d10v: convert to common sim engine logicMike Frysinger2015-11-151-118/+59
* sim: d10v: push down sd/cpu varsMike Frysinger2015-11-151-82/+101
* sim: sim-close: unify sim_close logicMike Frysinger2015-11-151-7/+0
* sim: cr16/d10v: localize translation funcsMike Frysinger2015-11-101-3/+3
* sim: arm/cr16/d10v/h8300/microblaze/sh: fill out sim-cpu pc fetch/store helpersMike Frysinger2015-04-171-0/+22
* sim: d10v: fix signal updatesMike Frysinger2015-04-021-8/+5
* sim: run: punt!Mike Frysinger2015-04-011-2/+0
* sim: d10v: convert to nrunMike Frysinger2015-03-301-115/+68
* sim: d10v: delete NEED_UI_LOOP_HOOK handlingMike Frysinger2015-03-301-19/+0
* sim: d10v: clean up misc warningsMike Frysinger2015-03-301-81/+27
* sim: d10v: use common configure optionsMike Frysinger2015-03-301-0/+8
* sim: constify arg to sim_do_commandMike Frysinger2014-03-101-1/+1
* sim: constify prog_nameMike Frysinger2014-03-051-1/+1
* remove PARAMS from simTom Tromey2014-01-071-10/+10
* include "config.h" instead of BFD's sysdep.h in d10v/interp.cJoel Brobecker2012-06-191-1/+13
* gdb/Pedro Alves2012-05-241-2/+2
* sim: constify sim_write source buffer (part 2)Mike Frysinger2010-04-141-1/+1
* * interp.c (sim_stop_reason): Fix typo.Nick Clifton2006-04-181-1/+1
* * remote-sim.c (gdbsim_wait): Pass target signal numbers toMark Mitchell2005-11-281-6/+3
* Index: mn10200/ChangeLogAndrew Cagney2004-06-291-3/+3
* 2003-06-22 Andrew Cagney <cagney@redhat.com>Andrew Cagney2003-06-221-36/+26
* Index: gdb/ChangeLogAndrew Cagney2003-05-071-18/+24
* Index: arm/ChangeLogAndrew Cagney2003-02-271-2/+2
* Fix for transfers across segments.Tom Rix2002-06-151-2/+3
* Move include/callback.h and include/remote-sim.h to include/gdb/.Andrew Cagney2002-06-091-2/+2
* Fix name of enum used in cast (sim_fetch_register, sim_store_register).Andrew Cagney2002-06-081-2/+2
* Fill-out d10v enum so that there are no ``=''.Andrew Cagney2002-06-011-56/+112
* 2002-05-28 Elena Zannoni <ezannoni@redhat.com>Elena Zannoni2002-05-281-0/+8
* * sim-d10v.h: Delete file. Moved to include/gdb/.Andrew Cagney2002-05-241-1/+1
* Removed a section of code that didn't do anything, but left values inJohn R. Moore2001-08-021-19/+0
* Add missing ChangeLog.Andrew Cagney2000-05-031-1/+2
* Add support for SIGILL (reserved-instruction-exception).Andrew Cagney2000-04-181-2/+7
* When SIM_HAVE_ENVIRONMENT: use sim_set_trace() to enable tracingAndrew Cagney2000-02-221-10/+2
* Report SIGBUS and halt simulation when ld/st detect a misaligned address.Andrew Cagney2000-02-091-2/+35
* import gdb-2000-01-05 snapshotJason Molenda2000-01-061-0/+1
* import gdb-1999-11-16 snapshotJason Molenda1999-11-171-288/+557
* import gdb-1999-09-13 snapshotJason Molenda1999-09-131-20/+75
* import gdb-19990422 snapshotStan Shebs1999-04-261-0/+18
* Initial creation of sourceware repositorygdb-4_18-branchpointStan Shebs1999-04-161-0/+1086
* Initial creation of sourceware repositoryStan Shebs1999-04-161-1069/+0
* Implement "dbt" and "rtd" instructions.Andrew Cagney1998-02-161-15/+25
* D10v memory map changed. Update.Andrew Cagney1998-02-101-136/+173
* * interp.c (UMEM_SEGMENTS): New define, set to 128.Fred Fish1998-01-221-54/+120
* * interp.c (sim_resume): Call do_2_short with LEFT_FIRST orFred Fish1997-12-021-26/+29
* Add LMA_P and DO_WRITE arguments to sim/common/sim-load.c:sim_load_file().Andrew Cagney1997-10-221-2/+21
View Lorry Controller Status