| Commit message (Expand) | Author | Age | Files | Lines |
|---|
| * | x86: drop vex_scalar_w_dq_mode | Jan Beulich | 2021-07-22 | 3 | -51/+41 |
| * | x86: drop xmm_m{b,w,d,q}_mode | Jan Beulich | 2021-07-22 | 4 | -164/+91 |
| * | x86: fold duplicate vector register printing code | Jan Beulich | 2021-07-22 | 1 | -74/+33 |
| * | x86: drop vex_mode and vex_scalar_mode | Jan Beulich | 2021-07-22 | 1 | -11/+7 |
| * | x86: correct EVEX.V' handling outside of 64-bit mode | Jan Beulich | 2021-07-22 | 1 | -4/+16 |
| * | x86: fold duplicate code in MOVSXD_Fixup() | Jan Beulich | 2021-07-22 | 1 | -16/+10 |
| * | x86: fold duplicate register printing code | Jan Beulich | 2021-07-22 | 1 | -105/+14 |
| * | x86-64: properly bounds-check %bnd<N> in OP_G() | Jan Beulich | 2021-07-22 | 1 | -1/+1 |
| * | x86-64: generalize OP_G()'s EVEX.R' handling | Jan Beulich | 2021-07-22 | 1 | -1/+8 |
| * | x86: correct VCVT{,U}SI2SD rounding mode handling | Jan Beulich | 2021-07-22 | 3 | -15/+3 |
| * | x86: drop OP_Mask() | Jan Beulich | 2021-07-22 | 4 | -48/+28 |
| * | x86: Add int1 as one byte opcode 0xf1 | H.J. Lu | 2021-07-14 | 3 | -1/+15 |
| * | Add changelog entries for last commit | Andreas Krebbel | 2021-07-07 | 1 | -0/+4 |
| * | IBM Z: Add another arch14 instruction | Andreas Krebbel | 2021-07-07 | 1 | -0/+2 |
| * | Updated translations (mainly Ukranian and French) triggered by creation of 2.... | Nick Clifton | 2021-07-05 | 3 | -709/+868 |
| * | Update version number and regenerate files | Nick Clifton | 2021-07-03 | 3 | -220/+254 |
| * | Add markers for 2.37 branch | Nick Clifton | 2021-07-03 | 1 | -0/+4 |
| * | Re: Fix minor NDS32 renaming snafu | Alan Modra | 2021-07-02 | 3 | -12/+21 |
| * | cgen: split GUILE setting out | Mike Frysinger | 2021-07-01 | 3 | -2/+10 |
| * | opcodes: constify & local meps macros | Mike Frysinger | 2021-07-01 | 2 | -5/+12 |
| * | opcodes: cleanup nds32 variables | Mike Frysinger | 2021-07-01 | 3 | -40/+57 |
| * | opcodes: constify & localize z80 opcodes | Mike Frysinger | 2021-07-01 | 2 | -2/+7 |
| * | opcodes: constify & scope microblaze opcodes | Mike Frysinger | 2021-07-01 | 3 | -11/+23 |
| * | opcodes: constify aarch64_opcode_tables | Mike Frysinger | 2021-07-01 | 3 | -3/+8 |
| * | opcodes: make use of __builtin_popcount when available | Andrew Burgess | 2021-06-22 | 2 | -0/+9 |
| * | picojava assembler and disassembler fixes | Alan Modra | 2021-06-22 | 2 | -2/+8 |
| * | ubsan: vax: pointer overflow | Alan Modra | 2021-06-19 | 2 | -1/+5 |
| * | Fix another strncpy warning | Alan Modra | 2021-06-19 | 2 | -1/+6 |
| * | powerpc: move cell "or rx,rx,rx" hints | Alan Modra | 2021-06-17 | 2 | -5/+10 |
| * | PR1202, mcore disassembler: wrong address loopt | Alan Modra | 2021-06-03 | 2 | -4/+10 |
| * | arc: Construct disassembler options dynamically | Shahab Vahedi | 2021-06-02 | 2 | -27/+161 |
| * | PowerPC table driven -Mraw disassembly | Alan Modra | 2021-05-29 | 3 | -1635/+1634 |
| * | MIPS/opcodes: Reorder legacy COP0, COP2, COP3 opcode instructions | Maciej W. Rozycki | 2021-05-29 | 2 | -66/+73 |
| * | MIPS/opcodes: Accurately record coprocessor opcode CPU/ISA membership | Maciej W. Rozycki | 2021-05-29 | 2 | -51/+61 |
| * | MIPS/opcodes: Remove DMFC3 and DMTC3 instructions | Maciej W. Rozycki | 2021-05-29 | 2 | -4/+5 |
| * | MIPS/opcodes: Disassemble the RFE instruction | Maciej W. Rozycki | 2021-05-29 | 2 | -2/+8 |
| * | MIPS/opcodes: Add legacy CP1 control register names | Maciej W. Rozycki | 2021-05-29 | 2 | -25/+47 |
| * | MIPS/opcodes: Do not use CP0 register names for control registers | Maciej W. Rozycki | 2021-05-29 | 4 | -17/+39 |
| * | MIPS/opcodes: Add TX39 CP0 register names | Maciej W. Rozycki | 2021-05-29 | 2 | -1/+19 |
| * | MIPS/opcodes: Free up redundant `g' operand code | Maciej W. Rozycki | 2021-05-29 | 2 | -4/+9 |
| * | microMIPS/opcodes: Refer FPRs rather than FCRs with DMTC1 | Maciej W. Rozycki | 2021-05-29 | 2 | -1/+6 |
| * | PowerPC: Add new xxmr and xxlnot extended mnemonics | Peter Bergner | 2021-05-27 | 2 | -0/+6 |
| * | Regen cris files | Alan Modra | 2021-05-25 | 5 | -30/+67 |
| * | opcodes: cris: move desc & opc files from sim/ | Mike Frysinger | 2021-05-24 | 9 | -4/+3403 |
| * | RISC-V: PR27814, Objdump crashes when disassembling a non-ELF RISC-V binary. | Job Noorman | 2021-05-18 | 2 | -10/+20 |
| * | arm: Fix bugs with MVE vmov from two GPRs to vector lanes | Alex Coplan | 2021-05-17 | 2 | -2/+14 |
| * | Fix an illegal memory access when attempting to disassemble a corrupt TIC30 b... | Nick Clifton | 2021-05-11 | 2 | -0/+9 |
| * | or1k: Implement relocation R_OR1K_GOT_AHI16 for gotha() | Stafford Horne | 2021-05-06 | 2 | -1/+11 |
| * | opcodes: xtensa: support branch visualization | Max Filippov | 2021-05-01 | 2 | -0/+15 |
| * | x86: optimize LEA | Jan Beulich | 2021-04-26 | 3 | -2/+7 |
