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* opcodes/riscv: style csr names as registersAndrew Burgess2022-10-041-1/+2
* RISC-V: Move supervisor instructions after all unprivileged onesTsukasa OI2022-10-031-32/+32
* RISC-V: Relax "fmv.[sdq]" requirementsTsukasa OI2022-09-301-3/+3
* RISC-V: fix build after "Add support for arbitrary immediate encoding formats"Jan Beulich2022-09-301-2/+2
* RISC-V: drop stray INSN_ALIAS flagsJan Beulich2022-09-301-3/+3
* RISC-V: re-arrange opcode table for consistent alias handlingJan Beulich2022-09-301-38/+38
* x86: correct build dependencies in opcodes/Jan Beulich2022-09-302-12/+16
* x86/Intel: restrict suffix derivationJan Beulich2022-09-304-7481/+7463
* PR29626, Segfault when disassembling ARM codeAlan Modra2022-09-301-63/+61
* RISC-V: Add Zawrs ISA extension supportChristoph Müllner2022-09-231-0/+4
* RISC-V: Add T-Head MemPair vendor extensionChristoph Müllner2022-09-221-0/+24
* RISC-V: Add support for literal instruction argumentsChristoph Müllner2022-09-221-0/+9
* RISC-V: Add T-Head MemIdx vendor extensionChristoph Müllner2022-09-221-0/+60
* RISC-V: Add T-Head FMemIdx vendor extensionChristoph Müllner2022-09-221-0/+10
* RISC-V: Add T-Head MAC vendor extensionChristoph Müllner2022-09-221-0/+8
* RISC-V: Add T-Head CondMov vendor extensionChristoph Müllner2022-09-221-0/+4
* RISC-V: Add T-Head Bitmanip vendor extensionChristoph Müllner2022-09-221-0/+17
* RISC-V: Add support for arbitrary immediate encoding formatsChristoph Müllner2022-09-221-0/+34
* RISC-V: Add T-Head SYNC vendor extensionChristoph Müllner2022-09-221-0/+7
* RISC-V: Add T-Head CMO vendor extensionChristoph Müllner2022-09-221-0/+25
* opcodes: SH fix bank register disassemble.Yoshinori Sato2022-09-222-0/+7
* RISC-V: Remove "b" operand type from disassemblerTsukasa OI2022-09-221-1/+0
* bfd: Stop using -Wstack-usage=262144 when built with ClangTsukasa OI2022-09-141-0/+18
* ubsan: arm-dis.c index out of boundsAlan Modra2022-09-141-1/+1
* ppc: Document the -mfuture and -Mfuture options and make them usablePeter Bergner2022-09-122-1/+3
* x86: avoid i386_dis_printf()'s staging area for a fair part of outputJan Beulich2022-09-121-20/+24
* opcodes: Add non-enum disassembler optionsTsukasa OI2022-09-063-0/+6
* RISC-V: Print highest address (-1) on the disassemblerTsukasa OI2022-09-021-6/+14
* RISC-V: PR29342, Fix RV32 disassembler address computationTsukasa OI2022-09-021-1/+7
* RISC-V: Add 'Zmmul' extension in assembler.Tsukasa OI2022-08-301-13/+13
* i386: Add MAX_OPERAND_BUFFER_SIZEH.J. Lu2022-08-161-3/+6
* x86: shorten certain template namesJan Beulich2022-08-161-26/+32
* x86: template-ize certain vector conversion insnsJan Beulich2022-08-163-181/+167
* x86: template-ize vector packed byte/word integer insnsJan Beulich2022-08-162-763/+692
* x86: re-order AVX512 S/G templatesJan Beulich2022-08-162-185/+182
* x86: template-ize vector packed dword/qword integer insnsJan Beulich2022-08-162-615/+518
* x86: template-ize packed/scalar vector floating point insnsJan Beulich2022-08-163-3577/+3345
* revert "x86: Also pass -P to $(CPP) when processing i386-opc.tbl"Jan Beulich2022-08-164-32/+56
* ppc/svp64: support svindex instructionDmitry Selyutin2022-08-111-0/+15
* ppc/svp64: support svremap instructionDmitry Selyutin2022-08-111-0/+20
* ppc/svp64: support svshape instructionDmitry Selyutin2022-08-111-0/+23
* ppc/svp64: support svstep instructionsDmitry Selyutin2022-08-111-0/+3
* ppc/svp64: support setvl instructionsDmitry Selyutin2022-08-111-0/+22
* ppc/svp64: introduce non-zero operand flagDmitry Selyutin2022-08-111-0/+3
* ppc/svp64: support LibreSOC architectureDmitry Selyutin2022-08-112-8/+14
* x86-64: adjust MOVQ to/from SReg attributesJan Beulich2022-08-092-3/+3
* x86: adjust MOVSD attributesJan Beulich2022-08-092-3/+3
* x86: fold AVX VGATHERDPD / VPGATHERDQJan Beulich2022-08-092-44/+8
* x86: allow use of broadcast with X/Y/Z-suffixed AVX512-FP16 insnsJan Beulich2022-08-092-54/+54
* x86/Intel: split certain AVX512-FP16 VCVT*2PH templatesJan Beulich2022-08-092-12/+108
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