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* aarch64: Add CSR PDEC instructionPrzemyslaw Wirkus2020-10-285-1417/+1430
* aarch64: Add WFET instruction for Armv8.7-aPrzemyslaw Wirkus2020-10-284-1347/+1353
* aarch64: Add DSB instruction Armv8.7-a variantPrzemyslaw Wirkus2020-10-2810-1455/+1513
* aarch64: Add basic support for armv8.7-a architecturePrzemyslaw Wirkus2020-10-281-0/+3
* CSKY: Change plsl.u16 to plsl.16.Cooper Qu2020-10-262-1/+5
* CSKY: Fix and add some instructions for VDSPV1.Cooper Qu2020-10-263-39/+231
* Change avxvnni disassembler output from {vex3} to {vex}Cui,Lili2020-10-262-1/+4
* [PATCH][GAS][AArch64] Define BRBE system registersPrzemyslaw Wirkus2020-10-221-0/+106
* aarch64: Define CSRE system registersPrzemyslaw Wirkus2020-10-221-0/+13
* opcodes/po/es.po: Remove the duplicated entryH.J. Lu2020-10-222-8/+4
* Fix printf formatting errors where "0x" is used as a prefix for a decimal num...Dr. David Alan Gilbert2020-10-222-2/+6
* Add AMD znver3 processor supportGanesh Gopalasubramanian2020-10-207-4213/+4494
* Enhancement for avx-vnni patchCui,Lili2020-10-166-11428/+11439
* x86: Support Intel AVX VNNIH.J. Lu2020-10-147-4539/+4705
* x86: Add support for Intel HRESET instructionLili Cui2020-10-147-4467/+4558
* x86: Support Intel UINTRLili Cui2020-10-147-4203/+8587
* x86: Remove the prefix byte from non-VEX/EVEX base_opcodeH.J. Lu2020-10-144-1077/+1136
* x86: Rename VexOpcode to OpcodePrefixH.J. Lu2020-10-135-2149/+2180
* Fix spelling mistakesSamanta Navarro2020-10-054-5/+11
* x86-64: Always display suffix for %LQ in 64bitH.J. Lu2020-10-052-1/+6
* x86: Clear modrm if not neededH.J. Lu2020-10-052-4/+15
* This patch introduces ETMv4 (Embedded Trace Macrocell) system registers for t...Przemyslaw Wirkus2020-09-282-3/+236
* This patch introduces ETE (Embedded Trace Extension) system registers for the...Przemyslaw Wirkus2020-09-282-0/+10
* This patch introduces TRBE (Trace Buffer Extension) system registers for the ...Przemyslaw Wirkus2020-09-282-0/+13
* ubsan: opcodes/csky-opc.h:929 shift exponent 536870912Alan Modra2020-09-263-28/+34
* Put together MOD_VEX_0F38* in i386-dis.c,Cui,Lili2020-09-252-62/+67
* csky/opcodes: enclose if body in curly bracesAndrew Burgess2020-09-242-2/+9
* Add support for Intel TDX instructions.Cui,Lili2020-09-247-4266/+4422
* CSKY: Add objdump option -M abi-names.Cooper Qu2020-09-233-180/+531
* Enable support to Intel Keylocker instructionsTerry Guo2020-09-237-4183/+4507
* rx-dis.c:103:3: suspicious concatenation of string literalsAlan Modra2020-09-212-8/+16
* bpf: xBPF SDIV, SMOD instructionsDavid Faust2020-09-185-6/+194
* opcodes/csky: return the default disassembler when there is no bfdAndrew Burgess2020-09-172-15/+22
* Tidy elf_symbol_fromAlan Modra2020-09-162-1/+5
* Stop symbols generated by the annobin gcc plugin from breaking the disassembl...Nick Clifton2020-09-102-0/+31
* CSKY: Add L2Cache instructions for CK860.Cooper Qu2020-09-102-109/+124
* CSKY: Add new arches while refine the cpu option process.Cooper Qu2020-09-101-0/+2
* Fix compile time warnings when building for the CSKY target on a 32-bit host.Nick Clifton2020-09-102-1/+6
* sprintf arg overlaps destinationAlan Modra2020-09-102-4/+8
* CSKY: Change mvtc and mulsw's ISA flag.Cooper Qu2020-09-092-2/+7
* CSKY: Add FPUV3 instructions, which supported by ck860f.Cooper Qu2020-09-093-2/+2133
* aarch64: Add support for Armv8-R system registersAlex Coplan2020-09-083-10/+93
* aarch64: Add support for Armv8-R DFB aliasAlex Coplan2020-09-085-1367/+1385
* aarch64: Add base support for Armv8-RAlex Coplan2020-09-082-0/+41
* ubsan: v850-opc.c:412 left shift cannot be representedAlan Modra2020-09-022-74/+81
* ubsan: i386-dis.cAlan Modra2020-09-022-13/+19
* ubsan: csky-dis.c:1038 left shift cannot be representedAlan Modra2020-09-022-1/+5
* ubsan: crx-dis.c:571 left shift of negative valueAlan Modra2020-09-022-74/+80
* ubsan: *-ibld.cAlan Modra2020-09-0216-60/+78
* ubsan: bfin-dis.c:160 shift exponent 32 is too largeAlan Modra2020-09-022-1/+5
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