| Commit message (Expand) | Author | Age | Files | Lines |
|---|
| ... | |
| * | x86: clean up after removal of support for gcc <= 2.8.1 | Jan Beulich | 2022-11-30 | 2 | -36/+5 |
| * | x86: drop FloatR | Jan Beulich | 2022-11-30 | 4 | -11255/+11187 |
| * | RISC-V: Better support for long instructions (disassembler) | Tsukasa OI | 2022-11-28 | 1 | -5/+9 |
| * | x86: widen applicability and use of CheckRegSize | Jan Beulich | 2022-11-24 | 2 | -14/+14 |
| * | x86: add missing CheckRegSize | Jan Beulich | 2022-11-24 | 2 | -6/+6 |
| * | x86: correct handling of LAR and LSL | Jan Beulich | 2022-11-24 | 3 | -6/+50 |
| * | PR16995, m68k coldfire emac immediate to macsr incorrect disassembly | Alan Modra | 2022-11-24 | 1 | -2/+2 |
| * | opcodes: Correct address for ARC's "isa_config" aux reg | Shahab Vahedi | 2022-11-22 | 2 | -1/+7 |
| * | opcodes: Define NoSuf in i386-opc.tbl | H.J. Lu | 2022-11-17 | 1 | -1847/+1848 |
| * | i386: Move i386_seg_prefixes to gas | H.J. Lu | 2022-11-17 | 2 | -11/+0 |
| * | RISC-V: Add T-Head Int vendor extension | Christoph Müllner | 2022-11-17 | 1 | -0/+4 |
| * | RISC-V: Add T-Head Fmv vendor extension | Christoph Müllner | 2022-11-17 | 1 | -0/+4 |
| * | Add AMD znver4 processor support | Tejas Joshi | 2022-11-15 | 6 | -4052/+4129 |
| * | aarch64: Add support for Common Short Sequence Compression extension | Andre Vieira | 2022-11-14 | 6 | -49/+166 |
| * | x86: fold special-operand insn attributes into a single enum | Jan Beulich | 2022-11-14 | 4 | -11219/+11210 |
| * | PowerPC64 paddi -Mraw | Alan Modra | 2022-11-12 | 1 | -10/+10 |
| * | x86: drop stray IsString from PadLock insns | Jan Beulich | 2022-11-11 | 2 | -32/+32 |
| * | [opcodes/arm] Fix potential null pointer dereferences | Luis Machado | 2022-11-10 | 1 | -1/+5 |
| * | RISC-V: xtheadfmemidx: Use fp register in mnemonics | Christoph Müllner | 2022-11-09 | 1 | -8/+8 |
| * | PowerPC: Add XSP operand define | Peter Bergner | 2022-11-08 | 1 | -5/+6 |
| * | x86: Correct wrong comments in vex_w_table | Haochen Jiang | 2022-11-08 | 1 | -1/+1 |
| * | Support Intel RAO-INT | Kong Lingling | 2022-11-08 | 6 | -4174/+4278 |
| * | opcodes/arm: silence compiler warning about uninitialized variable use | Andrew Burgess | 2022-11-04 | 1 | -1/+3 |
| * | Support Intel AVX-NE-CONVERT | konglin1 | 2022-11-04 | 6 | -4169/+4397 |
| * | i386: Rename <xy> template. | konglin1 | 2022-11-04 | 1 | -17/+18 |
| * | x86: drop bogus Tbyte | Jan Beulich | 2022-11-02 | 2 | -4/+4 |
| * | Support Intel MSRLIST | Hu, Lin1 | 2022-11-02 | 6 | -4161/+4237 |
| * | Support Intel WRMSRNS | Hu, Lin1 | 2022-11-02 | 6 | -4160/+4212 |
| * | Support Intel CMPccXADD | Haochen Jiang | 2022-11-02 | 6 | -4150/+4805 |
| * | Support Intel AVX-VNNI-INT8 | Cui,Lili | 2022-11-02 | 6 | -456/+612 |
| * | Support Intel AVX-IFMA | Hongyu Wang | 2022-11-02 | 7 | -4145/+4224 |
| * | opcodes/arm: don't pass non-string literal to printf like function | Andrew Burgess | 2022-11-01 | 1 | -2/+3 |
| * | opcodes/arm: silence compiler warning about uninitialized variable use | Andrew Burgess | 2022-11-01 | 1 | -1/+3 |
| * | opcodes/arm: add disassembler styling for arm | Andrew Burgess | 2022-11-01 | 2 | -1002/+1631 |
| * | opcodes/arm: use '@' consistently for the comment character | Andrew Burgess | 2022-11-01 | 1 | -48/+48 |
| * | x86: minor improvements to optimize_imm() (part III) | Jan Beulich | 2022-10-31 | 2 | -6/+0 |
| * | Updated Romainain translation for the binutils sub-directory and Swedish tran... | Nick Clifton | 2022-10-31 | 1 | -399/+475 |
| * | Support Intel PREFETCHI | Cui, Lili | 2022-10-31 | 6 | -4141/+4263 |
| * | RX assembler: switch arguments of thw MVTACGU insn. | Yoshinori Sato | 2022-10-31 | 3 | -8/+13 |
| * | RISC-V: Output mapping symbols with ISA string. | Nelson Chu | 2022-10-28 | 1 | -0/+9 |
| * | PowerPC: Add support for RFC02658 - MMA+ Outer-Product Instructions | Peter Bergner | 2022-10-27 | 1 | -1/+38 |
| * | PowerPC: Add support for RFC02653 - Dense Math Facility | Peter Bergner | 2022-10-27 | 2 | -26/+191 |
| * | x86: emit {evex} prefix when disassembling ambiguous AVX512VL insns | Jan Beulich | 2022-10-24 | 6 | -235/+271 |
| * | Support Intel AMX-FP16 | Cui,Lili | 2022-10-21 | 6 | -4088/+4139 |
| * | x86: re-work AVX-VNNI support | Jan Beulich | 2022-10-20 | 4 | -7025/+7021 |
| * | x86: Disable AVX-VNNI when disabling AVX2 | H.J. Lu | 2022-10-18 | 2 | -3/+3 |
| * | x86: correct CPU_AMX_{BF16,INT8}_FLAGS | Jan Beulich | 2022-10-18 | 2 | -4/+4 |
| * | Allow explicit size specifier for predicate operand of {sq, uq, }{incp, decp} | CaiJingtao | 2022-10-17 | 2 | -7/+17 |
| * | aarch64: Tweak handling of F_STRICT | Richard Sandiford | 2022-10-17 | 1 | -17/+8 |
| * | x86: properly decode EVEX.W for AVX512_4{FMAPS,VNNIW} insns | Jan Beulich | 2022-10-17 | 1 | -6/+6 |
