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* i386: Add MAX_OPERAND_BUFFER_SIZEH.J. Lu2022-08-161-3/+6
* x86: shorten certain template namesJan Beulich2022-08-161-26/+32
* x86: template-ize certain vector conversion insnsJan Beulich2022-08-163-181/+167
* x86: template-ize vector packed byte/word integer insnsJan Beulich2022-08-162-763/+692
* x86: re-order AVX512 S/G templatesJan Beulich2022-08-162-185/+182
* x86: template-ize vector packed dword/qword integer insnsJan Beulich2022-08-162-615/+518
* x86: template-ize packed/scalar vector floating point insnsJan Beulich2022-08-163-3577/+3345
* revert "x86: Also pass -P to $(CPP) when processing i386-opc.tbl"Jan Beulich2022-08-164-32/+56
* ppc/svp64: support svindex instructionDmitry Selyutin2022-08-111-0/+15
* ppc/svp64: support svremap instructionDmitry Selyutin2022-08-111-0/+20
* ppc/svp64: support svshape instructionDmitry Selyutin2022-08-111-0/+23
* ppc/svp64: support svstep instructionsDmitry Selyutin2022-08-111-0/+3
* ppc/svp64: support setvl instructionsDmitry Selyutin2022-08-111-0/+22
* ppc/svp64: introduce non-zero operand flagDmitry Selyutin2022-08-111-0/+3
* ppc/svp64: support LibreSOC architectureDmitry Selyutin2022-08-112-8/+14
* x86-64: adjust MOVQ to/from SReg attributesJan Beulich2022-08-092-3/+3
* x86: adjust MOVSD attributesJan Beulich2022-08-092-3/+3
* x86: fold AVX VGATHERDPD / VPGATHERDQJan Beulich2022-08-092-44/+8
* x86: allow use of broadcast with X/Y/Z-suffixed AVX512-FP16 insnsJan Beulich2022-08-092-54/+54
* x86/Intel: split certain AVX512-FP16 VCVT*2PH templatesJan Beulich2022-08-092-12/+108
* Don't use BFD_VMA_FMT in binutilsAlan Modra2022-08-041-3/+3
* x86: properly mark i386-only insnsJan Beulich2022-08-032-30/+30
* x86: also use D for MOVBEJan Beulich2022-08-033-19/+3
* x86: XOP shift insns don't really allow B suffixJan Beulich2022-08-022-20/+20
* x86: SKINIT with operand needs IgnoreSizeJan Beulich2022-08-012-2/+2
* opcodes: LoongArch: add "ret" instruction to reduce typingWANG Xuerui2022-08-011-0/+1
* opcodes: LoongArch: make all non-native jumps desugar to canonical b{lt/ge}[u...WANG Xuerui2022-08-011-19/+12
* Get rid of fprintf_vma and sprintf_vmaAlan Modra2022-08-015-50/+17
* libopcodes/aarch64: add support for disassembler stylingAndrew Burgess2022-07-293-177/+516
* x86: drop stray NoRex64 from KeyLocker insnsJan Beulich2022-07-292-6/+6
* libopcodes/ppc: add support for disassembler stylingAndrew Burgess2022-07-252-30/+86
* LoongArch:opcodes: Add new reloc types.liuzhensong2022-07-251-170/+242
* Add ChangeLog entry from previous commitPeter Bergner2022-07-211-0/+10
* PowerPC: Create new MMA instruction masks and use themPeter Bergner2022-07-211-33/+39
* x86: replace wrong attributes on VCVTDQ2PH{X,Y}Jan Beulich2022-07-212-4/+4
* x86/Intel: correct AVX512F scatter insn element sizesJan Beulich2022-07-212-8/+8
* Re: opcodes/arc: Implement style support in the disassemblerAlan Modra2022-07-201-1/+1
* opcodes/arc: Implement style support in the disassemblerClaudiu Zissulescu2022-07-183-46/+117
* x86: correct VMOVSH attributesJan Beulich2022-07-182-5/+5
* x86: re-order insn template fieldsJan Beulich2022-07-183-3720/+3728
* Regenerate with automake-1.15.1Alan Modra2022-07-093-901/+422
* libopcodes/s390: add support for disassembler stylingAndrew Burgess2022-07-082-16/+72
* Update version to 2.39.50 and regenerate filesNick Clifton2022-07-084-590/+1026
* Add markers for 2.39 branchNick Clifton2022-07-081-0/+4
* RISC-V: Added Zfhmin and Zhinxmin.Tsukasa OI2022-07-071-63/+63
* RISC-V: Fix disassembling Zfinx with -M numericTsukasa OI2022-07-071-1/+1
* x86: make D attribute usable for XOP and FMA4 insnsJan Beulich2022-07-063-706/+62
* opcodes/avr: Implement style support in the disassemblerMarcus Nilsson2022-07-043-10/+55
* x86: fold Disp32S and Disp32Jan Beulich2022-07-045-12883/+12886
* x86: restore masking of displacement kindsJan Beulich2022-07-042-12/+12
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