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* opcodes/avr: Implement style support in the disassemblerMarcus Nilsson2022-07-043-10/+55
* x86: fold Disp32S and Disp32Jan Beulich2022-07-045-12883/+12886
* x86: restore masking of displacement kindsJan Beulich2022-07-042-12/+12
* opcodes/aarch64: split off creation of comment text in disassemblerAndrew Burgess2022-06-292-8/+29
* x86: drop stray NoRex64 from XBEGINJan Beulich2022-06-292-2/+2
* drop XC16x bitsJan Beulich2022-06-2714-10784/+4
* RISC-V: Use single h extension to control hypervisor CSRs and instructions.Nelson Chu2022-06-221-19/+19
* x86: drop print_operand_value()'s "hex" parameterJan Beulich2022-06-151-55/+16
* x86: fix incorrect indirectionJan Beulich2022-06-131-1/+1
* x86: replace global scratch bufferJan Beulich2022-06-131-126/+97
* x86: avoid string copy when swapping Vex.W controlled operandsJan Beulich2022-06-131-6/+8
* x86: shrink prefix related disassembler state fieldsJan Beulich2022-06-131-27/+28
* x86: properly initialize struct instr_info instance(s)Jan Beulich2022-06-131-257/+235
* libopcodes: extend the styling within the i386 disassemblerAndrew Burgess2022-06-081-137/+286
* RISC-V: Add zhinx extension supports.jiawei2022-05-301-56/+56
* opcodes/i386: remove trailing whitespace from insns with zero operandsAndrew Burgess2022-05-271-5/+22
* Remove use of bfd_uint64_t and similarAlan Modra2022-05-273-4/+4
* x86: re-work AVX512 embedded rounding / SAEJan Beulich2022-05-272-11453/+853
* x86/Intel: adjust representation of embedded rounding / SAEJan Beulich2022-05-271-0/+17
* x86/Intel: adjust representation of embedded broadcastJan Beulich2022-05-271-4/+11
* opcodes: introduce BC field; fix iselDmitry Selyutin2022-05-251-2/+5
* ppc: extend opindex to 16 bitsDmitry Selyutin2022-05-251-6/+6
* RISC-V: Update zfinx implement with zicsr.Jia-Wei Chen2022-05-201-14/+14
* RISC-V: Remove RV128-only fmv instructionsTsukasa OI2022-05-201-2/+0
* x86: shrink op_riprelJan Beulich2022-05-181-18/+12
* RISC-V: Added half-precision floating-point v1.0 instructions.Nelson Chu2022-05-171-0/+65
* cgen: increase buffer for hash_insn_listAlan Modra2022-05-121-5/+5
* opcodes cgen: remove use of PTRAlan Modra2022-05-1129-1290/+1284
* opcodes: remove use of PTRAlan Modra2022-05-106-6/+6
* Fix multiple ubsan warnings in i386-dis.cAlan Modra2022-05-071-13/+13
* Move TILE-Gx files to TARGET64_LIBOPCODES_CFILESLuis Machado2022-05-052-6/+6
* Don't define ARCH_cris for BFD64Luis Machado2022-05-051-1/+1
* IBM zSystems: mgrk, mg first operand requires register pairAndreas Krebbel2022-05-052-2/+4
* opcodes: don't assume ELF in riscv, csky, rl78, mep disassemblersThomas Hebb2022-04-304-23/+22
* x86: VFPCLASSSH is Evex.LLIGJan Beulich2022-04-272-3/+2
* x86: VCMPSH is Evex.LLIGJan Beulich2022-04-192-98/+98
* x86: drop stray CheckRegSize from VFPCLASSPHJan Beulich2022-04-192-2/+2
* x86: correct and simplify NOP disassemblyJan Beulich2022-04-191-21/+9
* IBM zSystems: Add support for z16 as CPU name.Andreas Krebbel2022-04-072-1/+7
* opcodes/i386: partially implement disassembler style supportAndrew Burgess2022-04-042-24/+46
* opcodes/riscv: implement style support in the disassemblerAndrew Burgess2022-04-042-72/+122
* objdump/opcodes: add syntax highlighting to disassembler outputAndrew Burgess2022-04-042-1/+17
* x86: Remove bfd_arch_l1om and bfd_arch_k1omH.J. Lu2022-03-313-4/+2
* aarch64: Relax check for RNG system registersRichard Sandiford2022-03-311-1/+1
* RISC-V: correct FCVT.Q.L[U]Jan Beulich2022-03-291-2/+2
* libtool.m4: fix the NM="/nm/over/here -B/option/with/path" caseNick Alcock2022-03-251-7/+13
* x86: drop L1OM special case from disassemblerJan Beulich2022-03-241-6/+2
* gas:LoongArch: Fix segment error in compilation due to too long symbol name.liuzhensong2022-03-201-5/+10
* ubsan: loongarch : signed integer shift overflow.liuzhensong2022-03-201-6/+9
* x86: also fold remaining multi-vector-size shift insnsJan Beulich2022-03-182-375/+67
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