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* nds32: Rename __BIT() to N32_BIT().Kuan-Lin Chen2017-09-114-40/+46
* x86: Remove restriction on NOTRACK prefix positionH.J. Lu2017-09-092-16/+8
* Add updated French translations for opcodes and gprofNick Clifton2017-08-312-418/+786
* FT32: improve disassembly readabilityJames Bowman2017-08-302-7/+17
* [PowerPC VLE] Add SPE2 and EFS2 instructions supportAlexander Fedotov2017-08-243-12/+1239
* ppc-opc.c formattingAlan Modra2017-08-232-1089/+1101
* RISC-V: Mark "c.nop" as an aliasPalmer Dabbelt2017-08-222-1/+5
* [PowerPC VLE] Add LSP (Lightweight Signal Processing) instruction supportAlexander Fedotov2017-08-213-6/+920
* [ARM] Don't warn on REG_SP when used in CRC32 instructionsJiong Wang2017-08-092-11/+13
* Mark big and mach with ATTRIBUTE_UNUSEDH.J. Lu2017-08-072-1/+8
* GDB/opcodes: Remove arch/mach/endian disassembler assertionsMaciej W. Rozycki2017-08-072-12/+6
* Fix typos in error and option messages in OPCODES library.Nick Clifton2017-07-253-36/+75
* [AArch64] Fix the bit pattern order in the comments in auto-generated fileJiong Wang2017-07-243-1689/+1699
* S/390: Support z14 as CPU name.Andreas Krebbel2017-07-212-1/+7
* Update the German translation for the opcodes library.Nick Clifton2017-07-202-466/+890
* [ARC] Add SecureShield AUX registersclaziss2017-07-192-0/+21
* [ARC] Add SJLI instruction.Claudiu Zissulescu2017-07-193-1/+27
* [ARC] Add JLI support.John Eric Martin2017-07-194-2/+17
* Fix spelling typos.Yuri Chornovian2017-07-183-2/+8
* binutils/objdump: Fix disassemble for huge elf sectionsRavi Bangoria2017-07-142-3/+8
* Update PO filesAlan Modra2017-07-1216-875/+2049
* Mark generated cgen files read-onlyAlan Modra2017-07-1196-8/+211
* Move print_insn_XXX to an opcodes internal header, againAlan Modra2017-07-074-3/+9
* X86: Disassemble primary opcode map's group 2 ModRM.reg == 6 aliases correctlyBorislav Petkov2017-07-052-6/+10
* Fixup changelog entries for previous commitRamana Radhakrishnan2017-07-051-0/+5
* [Patch ARM] Support MVFR2 VFP Coprocessor register for ARMv8-ARamana Radhakrishnan2017-07-041-0/+4
* Regenerate configure.Tristan Gingold2017-07-042-10/+14
* Regenerate pot files.Tristan Gingold2017-07-032-133/+150
* MIPS/opcodes: Reorder LSA and DLSA instructionsMaciej W. Rozycki2017-06-302-3/+8
* MIPS: Add Imagination interAptiv MR2 MIPS32r3 processor support (ChangeLog)Maciej W. Rozycki2017-06-301-1/+1
* MIPS: Add microMIPS XPA supportMaciej W. Rozycki2017-06-302-0/+19
* MIPS: Add microMIPS R5 supportMaciej W. Rozycki2017-06-302-0/+8
* MIPS: Fix XPA base and Virtualization ASE instruction handlingMaciej W. Rozycki2017-06-303-24/+53
* MIPS/opcodes: Correctly combine ASE flags for ASE_MIPS16E2_MT calculationMaciej W. Rozycki2017-06-302-3/+20
* [ARC] Use FOR_EACH_DISASSEMBLER_OPTION to iterate over optionsAnton Kolesov2017-06-292-14/+11
* [ARC] Fix handling of cpu=... disassembler option valueAnton Kolesov2017-06-292-8/+14
* [AArch64] Add dot product support for AArch64 to binutilsTamar Christina2017-06-285-179/+265
* [ARM] Assembler and disassembler support Dot Product ExtensionJiong Wang2017-06-282-0/+10
* MIPS: Add Imagination interAptiv MR2 MIPS32r3 processor supportMaciej W. Rozycki2017-06-285-73/+152
* RISC-V: Fix SLTI disassemblyAndrew Waterman2017-06-232-2/+7
* x86: CET v2.0: Update incssp and setssbsyH.J. Lu2017-06-214-25/+41
* x86: CET v2.0: Rename savessp to saveprevsspH.J. Lu2017-06-214-3/+9
* x86: CET v2.0: Update NOTRACK prefixH.J. Lu2017-06-212-8/+13
* Prevent address violation when attempting to disassemble a corrupt score binary.Nick Clifton2017-06-192-0/+6
* Regen rx-decode.cAlan Modra2017-06-172-712/+716
* i386-dis: Check valid bnd registerH.J. Lu2017-06-152-0/+16
* Prevent address violation problem when disassembling corrupt aarch64 binary.Nick Clifton2017-06-152-0/+9
* Fix address violation when disassembling a corrupt RL78 binary.Nick Clifton2017-06-153-411/+424
* Prevent invalid array accesses when disassembling a corrupt bfin binary.Nick Clifton2017-06-152-4/+12
* Fix seg-fault when trying to disassemble a corrupt score binary.Nick Clifton2017-06-142-1/+7
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