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* x86: correct/improve TSX controlsJan Beulich2022-12-222-1/+32
| | | | | | TSXLDTRK takes RTM as a prereq. Additionally introduce an umbrella "tsx" extension option covering both RTM and HLE, paralleling the "abm" one we already have.
* x86: add dependencies on SVMEJan Beulich2022-12-222-7/+49
| | | | | | | | SEV-ES is an extension to SVME. SNP in turn is an extension to SEV-ES, and yet in turn RMPQUERY is a SNP extension. Note that cpu_arch[] has no SNP entry, so CPU_ANY_SNP_FLAGS remains unused (just like CPU_SNP_FLAGS already is).
* x86: add dependencies on VMXJan Beulich2022-12-222-2/+33
| | | | Both EPT and VMFUNC are extensions to VMX.
* x86: correct XSAVE* dependenciesJan Beulich2022-12-222-8/+10
| | | | | | | | Like various other features AMX-TILE takes XSAVE as a prereq. XSAVES, unconditionally using compacted format, in turn effectively takes XSAVEC as a prereq (an SDM clarification to this effect is in the works).
* x86: correct dependencies of a few AVX512 sub-featuresJan Beulich2022-12-222-10/+10
| | | | | | | Like AVX512-FP16, several other extensions require wider than 16-bit mask registers. As a result they take AVX512BW as a prereq, not (just) AVX512F. Which in turn points out wrong expectations in the noavx512-1 testcase.
* x86: add dependencies on AVX2Jan Beulich2022-12-222-9/+31
| | | | | Like AVX-VNNI both VAES and VPCLMUL take AVX2 as a prereq, for operating on up to 256-bit packed integer vectors.
* x86: correct SSE dependenciesJan Beulich2022-12-222-48/+92
| | | | | | SSE itself takes FXSR as a prereq. Like AES, PCLMUL, and SHA both GFNI and KL take SSE2 as a prereq, for operating on packed integers. And while correcting KL also record it as a prereq to WIDEKL.
* x86: re-work ISA extension dependency handlingJan Beulich2022-12-222-997/+883
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Getting both forward and reverse ISA dependencies right / consistent has been a permanent source of mistakes. Reduce what needs specifying manually to just the direct forward dependencies. Transitive forward dependencies as well as reverse ones are now derived and hence cannot go out of sync anymore (at least in the vast majority of cases; there are a few special cases to still take care of manually). In the course of this several CPU_ANY_*_FLAGS disappear, requiring adjustment to the assembler's cpu_arch[]. Note that to retain the correct reverse dependency of AVX512F wrt AVX512-VP2INTERSECT, the latter has the previously missing AVX512F prereq added. Note further that to avoid adding the following undue prereqs: * ATHLON, K8, and AMDFAM10 gain CMOV and FXSR, * IAMCU gains 387, auxiliary table entries (including a colon-separated modifier) are introduced in addition to the ones representing from converting the old table. To maintain forward-only dependencies between AVX (XOP) and SSE* (SSE4a) (i.e. "nosse" not disabling AVX), reverse dependency tracking is artifically suppressed. As a side effect disabling of SSE or SSE2 will now also disable AES, PCLMUL, and SHA (respective elements were missing from CPU_ANY_SSE2_FLAGS).
* x86: rename CheckRegSize to CheckOperandSizeJan Beulich2022-12-213-511/+511
| | | | | | While originally indeed used for register size checking only, the attribute has been used for memory operand size checking as well already for quite a while, with more such uses recently having been added.
* Re: x86: remove i386-opc.cAlan Modra2022-12-201-1/+0
| | | | Regen opcodes/po/POTFILES.in
* x86: omit Cpu prefixes from opcode tableJan Beulich2022-12-192-2220/+2238
| | | | | These enumerators can be used in only one specific field, and hence the Cpu prefix isn't needed ther for disambiguation / name space separation.
* x86: change representation of extension opcodeJan Beulich2022-12-163-2286/+2288
| | | | | | | Having a "None" field in the vast majority of entries is needlessly cluttering the overall table. Instead of this being a separate field, use a representation matching that of Intel SDM and AMD PM for the main use of the field: Append the value after a / as the separator.
* x86: further re-work insn/suffix recognition to also cover MOVSXJan Beulich2022-12-122-945/+892
| | | | | | | | | PR gas/29524 Having templates with a suffix explicitly present has always been quirky. After prior adjustment all that's left to also eliminate the anomaly from move-with-sign-extend is to consolidate the insn templates and to make may_need_pass2() cope (plus extend testsuite coverage).
* x86: drop (now) stray IsStringJan Beulich2022-12-122-26/+26
| | | | | | | | The need for them on the operand-less string insns has gone away with the removal of maybe_adjust_templates() and associated logic. Since i386_index_check() needs adjustment then anyway, take the opportunity and also simplify it, possible again as a result of said removal (plus the opcode template adjustments done here).
* x86: re-work insn/suffix recognitionJan Beulich2022-12-122-1290/+1118
| | | | | | | | | | | | | | | | | | | | | | | | | Having templates with a suffix explicitly present has always been quirky. Introduce a 2nd matching pass in case the 1st one couldn't find a suitable template _and_ didn't itself already need to trim off a suffix to find a match at all. This requires error reporting adjustments (albeit luckily fewer than I was afraid might be necessary), as errors previously reported during matching now need deferring until after the 2nd pass (because, obviously, we must not emit any error if the 2nd pass succeeds). While also related to PR gas/29524, it was requested that move-with-sign-extend be left as broken as it always was. PR gas/29525 Note that with the dropped CMPSD and MOVSD Intel Syntax string insn templates taking operands, mixed IsString/non-IsString template groups (with memory operands) cannot occur anymore. With that maybe_adjust_templates() becomes unnecessary (and is hence being removed). PR gas/29526 Note further that while the additions to the intel16 testcase aren't really proper Intel syntax, we've been permitting all of those except for the MOVD variant. The test therefore is to avoid re-introducing such an inconsistency.
* x86: revert disassembler parts of "x86: Allow 16-bit register source for LAR ↵Jan Beulich2022-12-121-2/+14
| | | | | | | | | | | | and LSL" This reverts the disassembler parts of 859aa2c86dc9 ("x86: Allow 16-bit register source for LAR and LSL"), adjusting testcases as necessary. That change was itself a partial revert of c9f5b96bdab0 ("x86: correct handling of LAR and LSL"), without actually saying so. While the earlier commit was properly agreed upon, the partial revert was not, and hence should not have been committed. This is even more so that the revert part of that change wasn't even necessary to address PR gas/29844.
* x86: generate template sets data at build timeJan Beulich2022-12-122-1/+2350
| | | | | | | | Speed up gas startup by avoiding runtime allocation of the instances of type "templates". At the same time cut the memory requirement to just very little over half (not even accounting for any overhead notes_alloc() may incur) by reusing the "end" slot of a preceding entry for the "start" slot of the subsequent one.
* x86: drop sentinel from i386_optab[]Jan Beulich2022-12-122-23/+0
| | | | | | | Now that the table is local to gas, ARRAY_SIZE() can be used to determine the end of the table. Re-arrange the processing loop in md_begin() accordingly, at the same time folding the two calls to notes_alloc() into just one.
* x86: remove i386-opc.cJan Beulich2022-12-125-36/+8
| | | | | | Remove the now empty i386-opc.c. To compensate, tie table generation in opcodes/ to the building of i386-dis.o, despite the file not really depending on the generated data.
* x86: instantiate i386_{op,reg}tab[] in gas instead of in libopcodesJan Beulich2022-12-124-13/+7
| | | | | | | | | | | | Unlike many other architectures, x86 does not share an opcode table between assembly and disassembly. Any consumer of libopcodes would only ever access one of the two. Since gas is the only consumer of the assembly data, move it there. While doing so mark respective entities "static" in i386-gen (we may want to do away with i386_regtab_size altogether). This also shrinks the number of relocations to be processed for libopcodes.so by about 30%.
* PowerPC: Add support for RFC02655 - Saturating Subtract InstructionPeter Bergner2022-12-071-0/+9
| | | | | | | | | | | | | | opcodes/ * ppc-opc.c (XOL): New define. (XOL_MASK): Likewise. (powerpc_opcodes): Add subfus, subfus., subwus, subwus., subdus, subdus. gas/ * testsuite/gas/ppc/rfc02655.s: New test. * testsuite/gas/ppc/rfc02655.d: Likewise * testsuite/gas/ppc/future-raw.s: Likewise. * testsuite/gas/ppc/future-raw.d: Likewise. * testsuite/gas/ppc/ppc.exp: Run them.
* PowerPC: Add support for RFC02656 - Enhanced Load Store with Length InstructionsPeter Bergner2022-12-071-0/+13
| | | | | | | | | | | | opcodes/ * ppc-opc.c (PPCVSXF): New define. (powerpc_opcodes): Add lxvrl, lxvrll, lxvprl, lxvprll, stxvrl, stxvrll, stxvprl, stxvprl. gas/ * testsuite/gas/ppc/rfc02656.s: New test. * testsuite/gas/ppc/rfc02656.d: Likewise. * testsuite/gas/ppc/ppc.exp: Run it.
* x86: Remove unnecessary vex.w check for xh_mode in disassemblerHaochen Jiang2022-12-061-17/+12
| | | | | | | | | For all the xh_mode usage in table, they are all using %XH, which will print "{bad}" while EVEX.W=1. This makes this vex.w check unnecessary. opcodes/ChangeLog: * i386-dis.c (OP_E_memory): Remove vex.w check for xh_mode.
* libopcodes/mips: add support for disassembler stylingAndrew Burgess2022-12-052-109/+201
| | | | | | | | | | | | | | | | | | This commit adds disassembler styling support for MIPS. After this commit objdump and GDB will style disassembler output. This is a pretty straight forward change, we switch to use the disassemble_info::fprintf_styled_func callback, and pass an appropriate style through as needed. No additional tricks were needed (compared to say i386, or ARM). Tested by running all of the objdump commands used by the gas testsuite and manually inspecting the styled output, everything looks reasonable, though I'm not a MIPS expert, so it is possible that I've missed some corner cases. Worst case though is that something will be styled incorrectly, the actual content should be unchanged. All the gas, ld, and binutils tests still pass for me.
* opcodes/mips: use .word/.short for undefined instructionsAndrew Burgess2022-12-051-3/+6
| | | | | | | | | | | | | While working on disassembler styling for MIPS, I noticed that undefined instructions are printed by the disassembler as raw number with no assembler directive prefix (e.g. without .word or .short). I think adding something like .word, or .short, helps to make it clearer the size of the value that is being displayed, and is inline with what many of the other libopcode disassemblers do. In this commit I've added the .word and .short directives, and updated all the tests that I spotted that failed as a result.
* x86: Allow 16-bit register source for LAR and LSLH.J. Lu2022-12-033-18/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Since LAR and LSL only access 16 bits of the source operand, regardless of operand size, allow 16-bit register source for LAR and LSL, and always disassemble LAR and LSL with 16-bit source operand. gas/ PR gas/29844 * testsuite/gas/i386/i386.s: Add tests for LAR and LSL. * testsuite/gas/i386/x86_64.s: Likewise. * testsuite/gas/i386/intelbad.s: Remove "lar/lsl eax, ax". * testsuite/gas/i386/i386-intel.d: Updated. * testsuite/gas/i386/i386.d: Likewise. * testsuite/gas/i386/intel-intel.d: Likewise. * testsuite/gas/i386/intel.d: Likewise. * testsuite/gas/i386/intelbad.l: Likewise. * testsuite/gas/i386/x86_64-intel.d: Likewise. * testsuite/gas/i386/x86_64.d: Likewise. opcodes/ PR gas/29844 * i386-dis.c (MOD_0F02): Removed. (MOD_0F03): Likewise. (dis386_twobyte): Restore larS and lslS. (mod_table): Remove MOD_0F02 and MOD_0F03. * i386-opc.tbl: Allow 16-bit register source for LAR and LSL. * i386-tbl.h: Regenerated.
* x86: drop most OPERAND_TYPE_* (and rework the rest)Jan Beulich2022-12-022-287/+0
| | | | | | | | | With the general use of C99 there's no need anymore to have i386-gen produce these. For more frequently used ones introduce local #define-s, while others are simply spelled out directly. While doing this move some static constants into more narrow scopes. Note that as a "side effect" this corrects type_names[]'es imm8s entry.
* x86: also use D for XCHG and TESTJan Beulich2022-12-022-57/+9
| | | | | | Leverage the C (commutative) attribute to also reduce the number of XCHG and TEST templates we have. This way the reg <-> r/m (and reg <-> reg for XCHG) forms can also be folded into a single template each, utilizing D.
* opcodes: Remove i386-init.h and i386-tbl.h from HFILESH.J. Lu2022-12-013-6/+0
| | | | | | | | | i386-init.h and i386-tbl.h are generated files. There is nothing to translate. Remove them from HFILES (POTFILES). * Makefile.am (HFILES): Remove i386-init.h and i386-tbl.h. * Makefile.in: Regenerated. * po/POTFILES.in: Likewise.
* x86: drop No_ldSufJan Beulich2022-12-014-11598/+11594
| | | | | With LONG_DOUBLE_MNEM_SUFFIX gone there'salso no use for No_ldSuf anymore.
* x86/Intel: drop LONG_DOUBLE_MNEM_SUFFIXJan Beulich2022-12-012-4/+4
| | | | | | With the removal of its use for FPU insns the suffix is now finally properly misnamed. Drop its use altogether, replacing it by a separate boolean instead.
* x86/Intel: restrict use of LONG_DOUBLE_MNEM_SUFFIXJan Beulich2022-12-012-8/+8
| | | | | | | | As a comment near the top of match_template() already says: We really only need this pseudo-suffix for far branch handling. Stop "deriving" it for floating point insns. (Don't bother renaming the now properly misnamed LONG_DOUBLE_MNEM_SUFFIX, to e.g. FAR_BRANCH_SUFFIX - it's going to disappear anyway.)
* x86: clean up after removal of support for gcc <= 2.8.1Jan Beulich2022-11-302-36/+5
| | | | | | | | | | | | | | | | | At the very least a comment in process_operands() is stale. Beyond that there are effectively two options: 1) It is possible that FADDP and FMULP were mistakenly not marked as being in need of dealing with the compiler anomaly, and hence the respective templates weren't removed at the time when they should have been. 2) It is also possible that there are indeed uses known beyond compiler generated output for these two commutative opcodes, and hence the templates need to stay. To be on the safe side assume 2: Update the comment and fold the templates into their "normal" ones (utilizing D), adjusting consuming code accordingly. For FMULP also add a comment paralleling a similar one FADDP has.
* x86: drop FloatRJan Beulich2022-11-304-11255/+11187
| | | | | | | | | | | | | | There are just 4 templates using it, which can be easily identified by other means, as D is set only on a very limited number of FPU templates. Also move the respective conditional out of the code path taken by all "reverse match" insns (it probably should have been this way already before, to avoid the one conditional in the common case). With this the templates which had FloatR dropped no longer differ from their AT&T syntax + mnemonic counterparts - the only difference is now which of the two would be recognized. For this, however, we don't need two templates - we can simply arrange the condition for setting Opcode_FloatR accordingly.
* RISC-V: Better support for long instructions (disassembler)Tsukasa OI2022-11-281-5/+9
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Commit bb996692bd96 ("RISC-V/gas: allow generating up to 176-bit instructions with .insn") tried to start supporting long instructions but it was insufficient. On the disassembler, correct ".byte" output was limited to the first 64-bits of an instruction. After that, zeroes are incorrectly printed. Note that, it only happens on ".byte" output (instruction part) and not on hexdump (data) part. For example, before this commit, hexdump and ".byte" produces different values: Assembly: .insn 22, 0xfedcba98765432100123456789abcdef55aa33cc607f objdump output example (before the fix): 10: 607f 33cc 55aa cdef .byte 0x7f, 0x60, 0xcc, 0x33, 0xaa, 0x55, 0xef, 0xcd, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 18: 89ab 4567 0123 3210 20: 7654 ba98 fedc Note that, after 0xcd (after first 64-bits of the target instruction), all ".byte" values are incorrectly printed as zero while hexdump prints correct instruction bits. To resolve this, this commit adds "packet" argument to support dumping instructions longer than 64-bits (to print correct instruction bits on ".byte"). This commit will be tested on the separate commit. Assembly: .insn 22, 0xfedcba98765432100123456789abcdef55aa33cc607f objdump output example (after the fix): 10: 607f 33cc 55aa cdef .byte 0x7f, 0x60, 0xcc, 0x33, 0xaa, 0x55, 0xef, 0xcd, 0xab, 0x89, 0x67, 0x45, 0x23, 0x01, 0x10, 0x32, 0x54, 0x76, 0x98, 0xba, 0xdc, 0xfe 18: 89ab 4567 0123 3210 20: 7654 ba98 fedc opcodes/ChangeLog: * riscv-dis.c (riscv_disassemble_insn): Print unknown instruction using the new argument packet. (riscv_disassemble_data): Add unused argument packet. (print_insn_riscv): Pass packet to the disassemble function.
* x86: widen applicability and use of CheckRegSizeJan Beulich2022-11-242-14/+14
| | | | | | | | | | | | | | | | | | | | | | | First of all make operand_type_register_match() apply to all sized operands, i.e. in Intel Syntax also to respective memory ones. This addresses gas wrongly accepting certain SIMD insns where register and memory operand sizes should match but don't. This apparently has affected all templates with one memory-only operand and one or more register ones, both permitting at least two sizes, due to CheckRegSize not taking effect. Then also add CheckRegSize to a couple of non-SIMD templates matching that same pattern of memory-only vs register operands. This replaces bogus (for Intel Syntax) diagnostics referring to a wrong suffix (when none was used at all) by "type mismatch" ones, just like already emitted for insns where the template allows a register operand alongside a memory one at any particular position. This also is a prereq to limiting (ideally eliminating in the long run) suffix "derivation" in Intel Syntax mode. While making the code adjustment also flip order of checks to do the cheaper one first in both cases.
* x86: add missing CheckRegSizeJan Beulich2022-11-242-6/+6
| | | | | | To properly and predictably determine operand size encoding (operand size or REX.W prefixes), consistent operand sizes need to be specified. Add CheckRegSize where this was previously missing.
* x86: correct handling of LAR and LSLJan Beulich2022-11-243-6/+50
| | | | | | | | Both uniformly only ever take 16-bit memory operands while at the same time requiring matching (in size) register operands, which then also should disassemble that way. This in particular requires splitting each of the templates for the assembler and separating decode of the register and memory forms in the disassembler.
* PR16995, m68k coldfire emac immediate to macsr incorrect disassemblyAlan Modra2022-11-241-2/+2
| | | | | | | | Mode/reg bits for these insns are 000 Dy, 001 Ay, and 111 100 for the move immediate. * m68k-opc.c (m68k_opcodes): Only accept 000 and 001 as mode for move reg to macsr/mask insns.
* opcodes: Correct address for ARC's "isa_config" aux regShahab Vahedi2022-11-222-1/+7
| | | | | | | | | | | This patch changes the address for "isa_config" auxiliary register from 0xC2 to the correct value 0xC1. Moreover, it only exists in arc700+ and not all ARCs. opcodes/ChangeLog: * arc-regs.h: Change isa_config address to 0xc1. isa_config exists for ARC700 and ARCV2 and not ARCALL.
* opcodes: Define NoSuf in i386-opc.tblH.J. Lu2022-11-171-1847/+1848
| | | | | | | | | | | Use NoSuf to replace No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf and add the explicit NoSuf to AddrPrefixOpReg in templates. * i386-opc.tbl (NoSuf): New macro. (AddrPrefixOpReg): Remove No_?Suf. Replace No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf with NoSuf in templates. Add NoSuf to AddrPrefixOpReg in templates.
* i386: Move i386_seg_prefixes to gasH.J. Lu2022-11-172-11/+0
| | | | | | | | | | | gas/ * config/tc-i386.c (i386_seg_prefixes): New. Moved from opcodes. opcodes/ * i386-opc.c (i386_seg_prefixes): Removed. * i386-opc.h (i386_seg_prefixes): Likewise.
* RISC-V: Add T-Head Int vendor extensionChristoph Müllner2022-11-171-0/+4
| | | | | | | | | | | | This patch adds the XTheadInt extension, which provides interrupt stack management instructions. The XTheadFmv extension is documented in the RISC-V toolchain contentions: https://github.com/riscv-non-isa/riscv-toolchain-conventions Co-developed-by: Lifang Xia <lifang_xia@linux.alibaba.com> Signed-off-by: Christoph Müllner <christoph.muellner@vrull.eu>
* RISC-V: Add T-Head Fmv vendor extensionChristoph Müllner2022-11-171-0/+4
| | | | | | | | | | | | This patch adds the XTheadFmv extension, which allows to access the upper 32 bits of a double-precision floating-point register in RV32. The XTheadFmv extension is documented in the RISC-V toolchain contentions: https://github.com/riscv-non-isa/riscv-toolchain-conventions Co-developed-by: Lifang Xia <lifang_xia@linux.alibaba.com> Signed-off-by: Christoph Müllner <christoph.muellner@vrull.eu>
* Add AMD znver4 processor supportTejas Joshi2022-11-156-4052/+4129
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | 2022-09-28 Tejas Joshi <TejasSanjay.Joshi@amd.com> gas/ * config/tc-i386.c (cpu_arch): Add znver4 ARCH and rmpquery SUBARCH. (md_assemble): Expand comment before swap_operands() with rmpquery. * doc/c-i386.texi: Add znver4. * testsuite/gas/i386/arch-14-1.d: New. * testsuite/gas/i386/arch-14-1.s: New. * testsuite/gas/i386/arch-14-znver4.d: New. * testsuite/gas/i386/i386.exp: Add new znver4 test cases. * testsuite/gas/i386/rmpquery.d: New. * testsuite/gas/i386/rmpquery.s: New. * testsuite/gas/i386/x86-64-arch-4-1.d: New. * testsuite/gas/i386/x86-64-arch-4-1.s: New. * testsuite/gas/i386/x86-64-arch-4-znver4.d: New. opcodes/ * i386-dis.c (x86_64_table): Add rmpquery. * i386-gen.c (cpu_flag_init): Add CPU_ZNVER4_FLAGS and CPU_RMPQUERY_FLAGS. (cpu_flags): Add CpuRMPQUERY. * i386-opc.h (enum): Add CpuRMPQUERY. (i386_cpu_flags): Add cpurmpquery. * i386-opc.tbl: Add rmpquery insn. * i386-init.h: Re-generated. * i386-tbl.h: Re-generated.
* aarch64: Add support for Common Short Sequence Compression extensionAndre Vieira2022-11-146-49/+166
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch adds support for the CSSC extension and its corresponding instructions: ABS, CNT, CTZ, SMAX, UMAX, SMIN, UMIN. gas/ChangeLog: * config/tc-aarch64.c (parse_operands): Handle new operand types. * doc/c-aarch64.texi: Document new extension. * testsuite/gas/aarch64/cssc.d: New test. * testsuite/gas/aarch64/cssc.s: New test. include/ChangeLog: * opcode/aarch64.h (AARCH64_FEATURE_CSSC): New feature Macro. (enum aarch64_opnd): New operand types. (enum aarch64_insn_class): New instruction class. opcodes/ChangeLog: * aarch64-asm-2.c: Regenerate. * aarch64-dis-2.c: Regenerate. * aarch64-opc-2.c: Regenerate. * aarch64-opc.c (operand_general_constraint_met_p): Update for new operand types. (aarch64_print_operand): Likewise. * aarch64-opc.h (enum aarch64_field_kind): Declare FLD_CSSC_imm8 field. * aarch64-tbl.h (aarch64_feature_cssc): Define new feature set. (CSSC): Define new feature set Macro. (CSSC_INSN): Define new instruction type. (aarch64_opcode_table): Add new instructions.
* x86: fold special-operand insn attributes into a single enumJan Beulich2022-11-144-11219/+11210
| | | | | | | | Attributes which aren't used together in any single insn template can be converted from individual booleans to a single enum, as was done for a few other attributes before. This is more space efficient. Collect together all attributes which express special operand constraints (and which fit the criteria for folding).
* PowerPC64 paddi -MrawAlan Modra2022-11-121-10/+10
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | On a testcase like pla 8,foo@pcrel disassembled with -Mpower10 results in 0: 00 00 10 06 pla r8,0 # 0 4: 00 00 00 39 0: R_PPC64_PCREL34 foo but with -Mpower10 -Mraw 0: 00 00 10 06 .long 0x6100000 0: R_PPC64_PCREL34 foo 4: 00 00 00 39 addi r8,0,0 The instruction is unrecognised due to the hack we have in extract_pcrel0 in order to disassemble paddi with RA0=0 and R=1 as pla. I could have just added "&& !(dialect & PPC_OPCODE_RAW)" to the condition in extract_pcrel0 under which *invalid is set, but went for this larger patch that reorders the extended insn pla to the more usual place before its underlying machine insn. (la is after addi because we never disassemble to la.) gas/ * testsuite/gas/ppc/raw.d, * testsuite/gas/ppc/raw.s: Add pla. opcodes/ * ppc-opc.c (extract_pcrel1): Rename from extract_pcrel0 and invert *invalid logic. (PCREL1): Rename from PCREL0. (prefix_opcodes): Sort pla before paddi, adjusting R operand for pla, paddi and psubi.
* x86: drop stray IsString from PadLock insnsJan Beulich2022-11-112-32/+32
| | | | | The need for IsString on the PadLock insns went away with the introduction of RepPrefixOk. Drop these leftovers.
* [opcodes/arm] Fix potential null pointer dereferencesLuis Machado2022-11-101-1/+5
| | | | | | | | | PR tdep/29598 As pointed out in the bug ticket, we have a couple potential null pointer dereferencing situations. Harden those. Bug: https://sourceware.org/bugzilla/show_bug.cgi?id=29598
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