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* x86: Remove bfd_arch_l1om and bfd_arch_k1omH.J. Lu2022-03-313-4/+2
* aarch64: Relax check for RNG system registersRichard Sandiford2022-03-311-1/+1
* RISC-V: correct FCVT.Q.L[U]Jan Beulich2022-03-291-2/+2
* libtool.m4: fix the NM="/nm/over/here -B/option/with/path" caseNick Alcock2022-03-251-7/+13
* x86: drop L1OM special case from disassemblerJan Beulich2022-03-241-6/+2
* gas:LoongArch: Fix segment error in compilation due to too long symbol name.liuzhensong2022-03-201-5/+10
* ubsan: loongarch : signed integer shift overflow.liuzhensong2022-03-201-6/+9
* x86: also fold remaining multi-vector-size shift insnsJan Beulich2022-03-182-375/+67
* x86: drop stray CheckRegSize from VEXTRACT{F,I}32X4Jan Beulich2022-03-182-4/+4
* x86: fold certain AVX2 templates into their AVX counterpartsJan Beulich2022-03-182-2284/+558
* RISC-V: Cache management instructionsTsukasa OI2022-03-181-0/+6
* RISC-V: Prefetch hint instructions and operand setTsukasa OI2022-03-182-0/+7
* x86: never set i386_cpu_flags' "unused" fieldJan Beulich2022-03-173-5/+10
* x86: unify CPU flag on/off processingJan Beulich2022-03-172-22/+11
* x86: drop L1OM/K1OM support from gasJan Beulich2022-03-174-5843/+5813
* x86: assorted IAMCU CPU checking fixesJan Beulich2022-03-172-2/+2
* opcodes: handle bfd_amdgcn_arch in configure scriptSimon Marchi2022-03-163-0/+7
* Delete PowerPC macro insn supportAlan Modra2022-03-161-18/+0
* PowerPC SPE/SPE2 aliases in powerpc_macrosAlan Modra2022-03-161-30/+27
* PowerPC VLE extended instructions in powerpc_macrosAlan Modra2022-03-161-13/+10
* PowerPC32 extended instructions in powerpc_macrosAlan Modra2022-03-161-25/+296
* PowerPC64 extended instructions in powerpc_macrosAlan Modra2022-03-161-19/+245
* PR28959, obdump doesn't disassemble mftb instructionAlan Modra2022-03-141-2/+3
* MIPS/opcodes: Fix alias annotation for branch instructionsMaciej W. Rozycki2022-03-063-7/+16
* RISC-V: Fix mask for some fcvt instructionsTsukasa OI2022-02-251-4/+4
* Updated Serbian translations for the bfd, gold, ld and opcodes directoriesNick Clifton2022-02-172-235/+275
* x86: Add has_sib to struct instr_infoH.J. Lu2022-02-151-8/+9
* microblaze: fix fsqrt collicion to build on glibc-2.35Sergei Trofimovich2022-02-143-2/+8
* Update Bulgarian, French, Romaniam and Ukranian translation for some of the s...Nick Clifton2022-01-244-923/+2834
* Regenerate Makefile.in files with automake 1.15.1H.J. Lu2022-01-231-1/+0
* Regenerate configure files with autoconf 2.69H.J. Lu2022-01-231-15/+3
* Change version number to 2.38.50 and regenerate filesNick Clifton2022-01-223-14/+31
* Add markers for 2.38 branchNick Clifton2022-01-221-0/+4
* drop old unused stamp-h.in fileMike Frysinger2022-01-211-1/+0
* Update the config.guess and config.sub files from the master repository and r...Nick Clifton2022-01-173-208/+244
* x86: adjust struct instr_info field typesJan Beulich2022-01-171-36/+39
* x86: drop index16 fieldJan Beulich2022-01-171-5/+3
* x86: drop most Intel syntax register name arraysJan Beulich2022-01-171-230/+119
* x86: fold variables in memory operand index handlingJan Beulich2022-01-171-19/+15
* x86: constify disassembler static dataJan Beulich2022-01-171-58/+58
* x86: drop ymmxmm_modeJan Beulich2022-01-141-16/+0
* x86: share yet more VEX table entries with EVEX decodingJan Beulich2022-01-144-209/+69
* x86: consistently use scalar_mode for AVX512-FP16 scalar insnsJan Beulich2022-01-142-31/+31
* x86: record further wrong uses of EVEX.bJan Beulich2022-01-141-0/+8
* x86: reduce AVX512 FP set of insns decoded through vex_w_table[]Jan Beulich2022-01-145-268/+42
* x86: reduce AVX512-FP16 set of insns decoded through vex_w_table[]Jan Beulich2022-01-144-137/+77
* aarch64: Add support for new SME instructionsRichard Sandiford2022-01-062-302/+338
* x86: drop NoAVX insn attributeJan Beulich2022-01-064-4520/+4516
* x86: drop NoAVX from POPCNTJan Beulich2022-01-062-2/+2
* x86: drop some "comm" template parametersJan Beulich2022-01-062-90/+90
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