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* Replace "if (x) free (x)" with "free (x)", opcodesAlan Modra2020-05-2120-194/+88
* [PATCH v2 0/9] RISC-V: Support version controling for ISA standard extensions...Nelson Chu2020-05-204-63/+331
* Power10 dcbf, sync, and wait extensions.Peter Bergner2020-05-192-26/+243
* or1k: Regenerate opcodes after removing 32-bit supportStafford Horne2020-05-199-1648/+1195
* Power10 VSX scalar min-max-compare quad precision operationsAlan Modra2020-05-112-0/+16
* Power10 VSX load/store rightmost element operationsAlan Modra2020-05-112-0/+21
* Power10 test lsb by byte operationAlan Modra2020-05-112-0/+5
* Power10 string operationsAlan Modra2020-05-112-0/+15
* Power10 Set boolean extensionPeter Bergner2020-05-112-0/+13
* Power10 bit manipulation operationsAlan Modra2020-05-112-1/+27
* Power10 VSX PCV generate operationsAlan Modra2020-05-112-0/+9
* Power10 VSX Mask Manipulation OperationsAlan Modra2020-05-112-1/+36
* Power10 Reduced precision outer product operationsAlan Modra2020-05-113-4/+231
* Power10 SIMD permute class operationsAlan Modra2020-05-112-3/+129
* Power10 128-bit binary integer operationsAlan Modra2020-05-112-0/+44
* Power10 VSX 32-byte storage accessAlan Modra2020-05-112-1/+44
* Power10 vector integer multiply, divide, modulo insnsAlan Modra2020-05-112-0/+23
* Power10 byte reverse instructionsPeter Bergner2020-05-112-0/+10
* Power10 Copy/Paste ExtensionsPeter Bergner2020-05-112-2/+37
* Power10 Add new L operand to the slbiag instructionPeter Bergner2020-05-112-1/+7
* PowerPC Default disassembler to -Mpower10Alan Modra2020-05-112-1/+5
* PowerPC Rename powerxx to power10Alan Modra2020-05-113-30/+41
* Updated French translation for the ld sub-directory and an update Spanish tra...Nick Clifton2020-05-112-349/+455
* AArch64: add GAS support for UDF instructionAlex Coplan2020-04-308-2477/+2541
* Also use unsigned 8-bit immediate values for the LDRC and SETRC insns.Nick Clifton2020-04-292-2/+8
* Updated Serbian translation for the binutils sub-directory, and Swedish trans...Nick Clifton2020-04-292-351/+457
* Fix the disassmbly of SH instructions which have an unsigned 8-bit immediate ...Nick Clifton2020-04-293-18/+31
* Disallow PC relative for CMPI on MC68000/10Andreas Schwab2020-04-212-6/+18
* [AArch64, Binutils] Add missing TSB instructionSudakshina Das2020-04-2010-1376/+1422
* [AArch64, Binutils] Make hint space instructions valid for Armv8-aSudakshina Das2020-04-205-1370/+1369
* [PATCH v2] binutils: arm: Fix disassembly of conditional VDUPs.Fredrik Strupe2020-04-172-10/+53
* cpu,gas,opcodes: support for eBPF JMP32 instruction classDavid Faust2020-04-165-13/+515
* Add support for intel TSXLDTRK instructions$Cui,Lili2020-04-077-4154/+4234
* Add support for intel SERIALIZE instructionLiliCui2020-04-027-4151/+4205
* Re: H8300 use of uninitialised valueAlan Modra2020-03-264-126/+152
* Re: ARC: Use of uninitialised valueAlan Modra2020-03-262-2/+6
* Uninitialised memory read in z80-dis.cAlan Modra2020-03-252-0/+5
* H8300 use of uninitialised valueAlan Modra2020-03-222-6/+33
* ARC: Use of uninitialised valueAlan Modra2020-03-222-3/+10
* NS32K arg_bufs uninitialisedAlan Modra2020-03-222-9/+17
* s12z disassembler tidyAlan Modra2020-03-223-315/+760
* metag uninitialized memory readAlan Modra2020-03-202-2/+13
* NDS32 disassembly of odd sized sectionsAlan Modra2020-03-202-9/+22
* PowerPC disassembly of odd sized sectionsAlan Modra2020-03-202-10/+25
* Replace a couple of assertions in the BFD library that can be triggered by at...Nick Clifton2020-03-171-0/+5
* Fix a small set of Z80 problems.Sergey Belyashov2020-03-171-19/+8
* x86-64: correct mis-named X86_64_0D enumeratorJan Beulich2020-03-132-3/+8
* x86: Also pass -P to $(CPP) when processing i386-opc.tblH.J. Lu2020-03-093-2/+7
* x86: use template for AVX512 integer comparison insnsJan Beulich2020-03-093-80/+48
* x86: use template for XOP integer comparison, shift, and rotate insnsJan Beulich2020-03-093-268/+187
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