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path: root/opcodes/riscv-opc.c
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* RISC-V: Dump vset[i]vli immediate as numbers once vsew or vlmul is reserved.Nelson Chu2021-11-301-2/+2
* RISC-V: Add instructions and operand set for z[fdq]inxjiawei2021-11-181-148/+148
* RISC-V: Support rvv extension with released version 1.0.Nelson Chu2021-11-171-0/+826
* RISC-V: Scalar crypto instructions and operand set.jiawei2021-11-161-20/+72
* RISC-V: Support aliases for Zbs instructionsPhilipp Tomsich2021-10-071-0/+4
* RISC-V: Add support for Zbs instructionsPhilipp Tomsich2021-10-071-0/+9
* RISC-V: Split Zb[abc] into commented sectionsPhilipp Tomsich2021-10-071-0/+6
* RISC-V: compress "addi d,CV,z" to "c.mv d,CV"Lifang Xia2021-04-161-0/+1
* RISC-V : Support bitmanip-0.93 ZBA/ZBB/ZBC instructionsKuan-Lin Chen2021-03-161-4/+49
* RISC-V: PR27158, fixed UJ/SB types and added CSS/CL/CS types for .insn.Nelson Chu2021-02-191-12/+22
* RISC-V: Add bfd/cpu-riscv.h to support all spec versions controlling.Nelson Chu2021-02-181-87/+0
* RISC-V: Removed the v0.93 bitmanip ZBA/ZBB/ZBC instructions.Nelson Chu2021-02-041-53/+4
* RISC-V: Indent and GNU coding standards tidy, also aligned the code.Nelson Chu2021-01-151-710/+707
* RISC-V: Comments tidy and improvement.Nelson Chu2021-01-151-17/+16
* RISC-V: Add pause hint instruction.Philipp Tomsich2021-01-071-0/+3
* RISC-V: Support riscv bitmanip frozen ZBA/ZBB/ZBC instructions (v0.93).Claire Xenia Wolf2021-01-071-4/+53
* Update year range in copyright notice of binutils filesAlan Modra2021-01-011-1/+1
* RISC-V: Add sext.[bh] and zext.[bhw] pseudo instructions.Nelson Chu2020-12-101-0/+5
* RISC-V: Control fence.i and csr instructions by zifencei and zicsr.Nelson Chu2020-12-101-20/+20
* RISC-V: Remove the unimplemented extensions.Nelson Chu2020-12-011-11/+0
* RISC-V: Add zifencei and prefixed h class extensions.Nelson Chu2020-12-011-0/+3
* RISC-V: Report warning when linking the objects with different priv specs.Nelson Chu2020-06-221-50/+0
* RISC-V: Drop the privileged spec v1.9 support.Nelson Chu2020-06-121-1/+0
* RISC-V: Fix the error when building RISC-V linux native gdbserver.Nelson Chu2020-06-031-8/+8
* [PATCH v2 0/9] RISC-V: Support version controling for ISA standard extensions...Nelson Chu2020-05-201-0/+144
* RISC-V: Convert the ADD/ADDI to the compressed MV/LI if RS1 is zero.Jim Wilson2020-02-191-0/+2
* Update year range in copyright notice of binutils filesAlan Modra2020-01-011-1/+1
* RISC-V: Support the INSN_CLASS.*F.* classes for .insn directive.Jim Wilson2019-11-121-60/+60
* RISC-V: Gate opcode tables by enum rather than string.Jim Wilson2019-09-171-658/+658
* RISC-V: Fix minor issues with FP csr instructions.Jim Wilson2019-07-301-16/+16
* Kito's 5-part patch set to improve .insn support.Jim Wilson2019-07-051-4/+26
* RISC-V: Compress 3-operand beq/bne against x0.Jim Wilson2019-02-081-0/+2
* Update year range in copyright notice of binutils filesAlan Modra2019-01-011-1/+1
* RISC-V: Fix 4-arg add parsing.Jim Wilson2018-12-071-1/+1
* RISC-V: Add missing c.unimp instruction.Jim Wilson2018-11-291-1/+2
* RISC-V: Add .insn CA support.Jim Wilson2018-11-271-2/+7
* RISC-V: Add fence.tso instructionPalmer Dabbelt2018-10-021-0/+1
* RISC-V: bge[u] should get higher priority than ble[u].Jim Wilson2018-09-171-2/+2
* RISC-V: Correct the requirement of compressed floating point instructionsJim Wilson2018-08-311-16/+16
* RISC-V: Allow instruction require more than one extensionJim Wilson2018-08-301-629/+629
* RISC-V: Set insn info fields correctly when disassembling.Jim Wilson2018-07-301-178/+178
* RISC-V: Accept constant operands in la and llaSebastian Huber2018-06-201-2/+2
* RISC-V: Add missing hint instructions from RV128I.Jim Wilson2018-05-081-9/+45
* RISC-V: Add .insn support.Jim Wilson2018-03-141-0/+74
* RISC-V: Fix bug in prior addi/c.nop patch.Jim Wilson2018-01-171-1/+1
* RISC-V: Add support for addi that compresses to c.nop.Jim Wilson2018-01-151-0/+8
* Update year range in copyright notice of binutils filesAlan Modra2018-01-031-1/+1
* RISC-V: Add compressed instruction hints, and a few misc cleanups.Jim Wilson2017-12-201-13/+35
* Add missing RISC-V fsrmi and fsflagsi instructions.Jim Wilson2017-12-131-0/+4
* RISC-V: Fix disassembly of c.addi4spn, c.addi16sp, c.lui when imm=0Andrew Waterman2017-10-241-7/+23
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