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path: root/opcodes/riscv-opc.c
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* RISC-V: Move standard hints before all instructionsTsukasa OI2022-10-141-4/+8
* RISC-V: Move certain arrays to riscv-opc.cTsukasa OI2022-10-141-0/+13
* RISC-V: Renamed INSN_CLASS for floating point in integer extensions.Nelson Chu2022-10-041-222/+222
* RISC-V: Move supervisor instructions after all unprivileged onesTsukasa OI2022-10-031-32/+32
* RISC-V: Relax "fmv.[sdq]" requirementsTsukasa OI2022-09-301-3/+3
* RISC-V: drop stray INSN_ALIAS flagsJan Beulich2022-09-301-3/+3
* RISC-V: re-arrange opcode table for consistent alias handlingJan Beulich2022-09-301-38/+38
* RISC-V: Add Zawrs ISA extension supportChristoph Müllner2022-09-231-0/+4
* RISC-V: Add T-Head MemPair vendor extensionChristoph Müllner2022-09-221-0/+24
* RISC-V: Add T-Head MemIdx vendor extensionChristoph Müllner2022-09-221-0/+60
* RISC-V: Add T-Head FMemIdx vendor extensionChristoph Müllner2022-09-221-0/+10
* RISC-V: Add T-Head MAC vendor extensionChristoph Müllner2022-09-221-0/+8
* RISC-V: Add T-Head CondMov vendor extensionChristoph Müllner2022-09-221-0/+4
* RISC-V: Add T-Head Bitmanip vendor extensionChristoph Müllner2022-09-221-0/+17
* RISC-V: Add T-Head SYNC vendor extensionChristoph Müllner2022-09-221-0/+7
* RISC-V: Add T-Head CMO vendor extensionChristoph Müllner2022-09-221-0/+25
* RISC-V: Add 'Zmmul' extension in assembler.Tsukasa OI2022-08-301-13/+13
* RISC-V: Added Zfhmin and Zhinxmin.Tsukasa OI2022-07-071-63/+63
* RISC-V: Use single h extension to control hypervisor CSRs and instructions.Nelson Chu2022-06-221-19/+19
* RISC-V: Add zhinx extension supports.jiawei2022-05-301-56/+56
* RISC-V: Update zfinx implement with zicsr.Jia-Wei Chen2022-05-201-14/+14
* RISC-V: Remove RV128-only fmv instructionsTsukasa OI2022-05-201-2/+0
* RISC-V: Added half-precision floating-point v1.0 instructions.Nelson Chu2022-05-171-0/+65
* RISC-V: correct FCVT.Q.L[U]Jan Beulich2022-03-291-2/+2
* RISC-V: Cache management instructionsTsukasa OI2022-03-181-0/+6
* RISC-V: Prefetch hint instructions and operand setTsukasa OI2022-03-181-0/+3
* RISC-V: Fix mask for some fcvt instructionsTsukasa OI2022-02-251-4/+4
* Update year range in copyright notice of binutils filesAlan Modra2022-01-021-1/+1
* RISC-V: Hypervisor ext: support Privileged Spec 1.12Vineet Gupta2021-12-241-0/+21
* RISC-V: Support svinval extension with frozen version 1.0.Nelson Chu2021-12-161-0/+7
* RISC-V: Dump vset[i]vli immediate as numbers once vsew or vlmul is reserved.Nelson Chu2021-11-301-2/+2
* RISC-V: Add instructions and operand set for z[fdq]inxjiawei2021-11-181-148/+148
* RISC-V: Support rvv extension with released version 1.0.Nelson Chu2021-11-171-0/+826
* RISC-V: Scalar crypto instructions and operand set.jiawei2021-11-161-20/+72
* RISC-V: Support aliases for Zbs instructionsPhilipp Tomsich2021-10-071-0/+4
* RISC-V: Add support for Zbs instructionsPhilipp Tomsich2021-10-071-0/+9
* RISC-V: Split Zb[abc] into commented sectionsPhilipp Tomsich2021-10-071-0/+6
* RISC-V: compress "addi d,CV,z" to "c.mv d,CV"Lifang Xia2021-04-161-0/+1
* RISC-V : Support bitmanip-0.93 ZBA/ZBB/ZBC instructionsKuan-Lin Chen2021-03-161-4/+49
* RISC-V: PR27158, fixed UJ/SB types and added CSS/CL/CS types for .insn.Nelson Chu2021-02-191-12/+22
* RISC-V: Add bfd/cpu-riscv.h to support all spec versions controlling.Nelson Chu2021-02-181-87/+0
* RISC-V: Removed the v0.93 bitmanip ZBA/ZBB/ZBC instructions.Nelson Chu2021-02-041-53/+4
* RISC-V: Indent and GNU coding standards tidy, also aligned the code.Nelson Chu2021-01-151-710/+707
* RISC-V: Comments tidy and improvement.Nelson Chu2021-01-151-17/+16
* RISC-V: Add pause hint instruction.Philipp Tomsich2021-01-071-0/+3
* RISC-V: Support riscv bitmanip frozen ZBA/ZBB/ZBC instructions (v0.93).Claire Xenia Wolf2021-01-071-4/+53
* Update year range in copyright notice of binutils filesAlan Modra2021-01-011-1/+1
* RISC-V: Add sext.[bh] and zext.[bhw] pseudo instructions.Nelson Chu2020-12-101-0/+5
* RISC-V: Control fence.i and csr instructions by zifencei and zicsr.Nelson Chu2020-12-101-20/+20
* RISC-V: Remove the unimplemented extensions.Nelson Chu2020-12-011-11/+0
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