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path: root/opcodes/i386-tbl.h
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* Add AMD znver4 processor supportTejas Joshi2022-11-151-3838/+3868
* x86: fold special-operand insn attributes into a single enumJan Beulich2022-11-141-11176/+11176
* x86: drop stray IsString from PadLock insnsJan Beulich2022-11-111-16/+16
* Support Intel RAO-INTKong Lingling2022-11-081-3923/+3983
* Support Intel AVX-NE-CONVERTkonglin12022-11-041-3914/+4064
* x86: drop bogus TbyteJan Beulich2022-11-021-2/+2
* Support Intel MSRLISTHu, Lin12022-11-021-3913/+3939
* Support Intel WRMSRNSHu, Lin12022-11-021-3913/+3926
* Support Intel CMPccXADDHaochen Jiang2022-11-021-3885/+4395
* Support Intel AVX-VNNI-INT8Cui,Lili2022-11-021-390/+492
* Support Intel AVX-IFMAHongyu Wang2022-11-021-3888/+3922
* Support Intel PREFETCHICui, Lili2022-10-311-3887/+3913
* Support Intel AMX-FP16Cui,Lili2022-10-211-3854/+3871
* x86: re-work AVX-VNNI supportJan Beulich2022-10-201-7011/+7011
* x86/Intel: restrict suffix derivationJan Beulich2022-09-301-7318/+7318
* x86: template-ize certain vector conversion insnsJan Beulich2022-08-161-80/+97
* x86: template-ize vector packed byte/word integer insnsJan Beulich2022-08-161-618/+618
* x86: re-order AVX512 S/G templatesJan Beulich2022-08-161-157/+157
* x86: template-ize vector packed dword/qword integer insnsJan Beulich2022-08-161-419/+419
* x86: template-ize packed/scalar vector floating point insnsJan Beulich2022-08-161-3143/+3143
* x86-64: adjust MOVQ to/from SReg attributesJan Beulich2022-08-091-2/+2
* x86: adjust MOVSD attributesJan Beulich2022-08-091-2/+2
* x86: fold AVX VGATHERDPD / VPGATHERDQJan Beulich2022-08-091-40/+6
* x86: allow use of broadcast with X/Y/Z-suffixed AVX512-FP16 insnsJan Beulich2022-08-091-36/+36
* x86/Intel: split certain AVX512-FP16 VCVT*2PH templatesJan Beulich2022-08-091-6/+96
* x86: properly mark i386-only insnsJan Beulich2022-08-031-21/+21
* x86: also use D for MOVBEJan Beulich2022-08-031-16/+1
* x86: XOP shift insns don't really allow B suffixJan Beulich2022-08-021-16/+16
* x86: SKINIT with operand needs IgnoreSizeJan Beulich2022-08-011-1/+1
* x86: drop stray NoRex64 from KeyLocker insnsJan Beulich2022-07-291-3/+3
* x86: replace wrong attributes on VCVTDQ2PH{X,Y}Jan Beulich2022-07-211-2/+2
* x86/Intel: correct AVX512F scatter insn element sizesJan Beulich2022-07-211-4/+4
* x86: correct VMOVSH attributesJan Beulich2022-07-181-3/+3
* x86: re-order insn template fieldsJan Beulich2022-07-181-3715/+3715
* x86: make D attribute usable for XOP and FMA4 insnsJan Beulich2022-07-061-656/+34
* x86: fold Disp32S and Disp32Jan Beulich2022-07-041-12785/+12800
* x86: drop stray NoRex64 from XBEGINJan Beulich2022-06-291-1/+1
* x86: re-work AVX512 embedded rounding / SAEJan Beulich2022-05-271-10941/+591
* x86: VFPCLASSSH is Evex.LLIGJan Beulich2022-04-271-1/+1
* x86: VCMPSH is Evex.LLIGJan Beulich2022-04-191-94/+94
* x86: drop stray CheckRegSize from VFPCLASSPHJan Beulich2022-04-191-1/+1
* x86: also fold remaining multi-vector-size shift insnsJan Beulich2022-03-181-339/+50
* x86: drop stray CheckRegSize from VEXTRACT{F,I}32X4Jan Beulich2022-03-181-2/+2
* x86: fold certain AVX2 templates into their AVX counterpartsJan Beulich2022-03-181-2092/+462
* x86: drop L1OM/K1OM support from gasJan Beulich2022-03-171-5440/+5440
* x86: drop NoAVX insn attributeJan Beulich2022-01-061-4472/+4472
* x86: drop NoAVX from POPCNTJan Beulich2022-01-061-1/+1
* x86: drop some "comm" template parametersJan Beulich2022-01-061-48/+48
* x86: templatize FMA insn templatesJan Beulich2022-01-061-747/+747
* Update year range in copyright notice of binutils filesAlan Modra2022-01-021-1/+1
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