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path: root/opcodes/i386-tbl.h
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* [PATCH 1/2] Enable Intel AVX512_FP16 instructionsCui,Lili2021-08-051-15911/+23504
* x86: Add int1 as one byte opcode 0xf1H.J. Lu2021-07-141-0/+13
* x86: optimize LEAJan Beulich2021-04-261-1/+1
* x86: adjust st(<N>) parsingJan Beulich2021-03-301-5/+1
* x86: move some opcode table entriesJan Beulich2021-03-291-459/+459
* x86: VPSADBW's source operands are also commutativeJan Beulich2021-03-291-3/+3
* x86: fold SSE2AVX and their base MMX/SSE templatesJan Beulich2021-03-291-356/+356
* x86: derive opcode encoding space attribute from base opcodeJan Beulich2021-03-291-1596/+1596
* x86-64: don't accept supposedly disabled MOVQ formsJan Beulich2021-03-261-2/+2
* x86: fix AMD Zen3 insnsJan Beulich2021-03-251-1/+52
* x86: derive opcode length from opcode valueJan Beulich2021-03-241-4034/+4034
* x86: derive mandatory prefix attribute from base opcodeJan Beulich2021-03-241-4974/+4974
* x86: don't use opcode_length to identify pseudo prefixesJan Beulich2021-03-241-11/+11
* x86: re-number PREFIX_0X<nn>Jan Beulich2021-03-231-148/+148
* x86: re-order two fields of struct insn_templateJan Beulich2021-03-231-12099/+12099
* x86: split opcode prefix and opcode space representationJan Beulich2021-03-231-7156/+7156
* x86: fold some prefix related attributes into a single oneJan Beulich2021-03-091-7438/+7438
* x86-64: make SYSEXIT handling similar to SYSRET'sJan Beulich2021-03-091-1/+1
* x86: CVTPI2PD has special behaviorJan Beulich2021-02-161-1/+31
* Update year range in copyright notice of binutils filesAlan Modra2021-01-011-1/+1
* Add AMD znver3 processor supportGanesh Gopalasubramanian2020-10-201-4020/+4165
* Enhancement for avx-vnni patchCui,Lili2020-10-161-11177/+11177
* x86: Support Intel AVX VNNIH.J. Lu2020-10-141-4292/+4360
* x86: Add support for Intel HRESET instructionLili Cui2020-10-141-4274/+4287
* x86: Support Intel UINTRLili Cui2020-10-141-4010/+8085
* x86: Remove the prefix byte from non-VEX/EVEX base_opcodeH.J. Lu2020-10-141-730/+730
* x86: Rename VexOpcode to OpcodePrefixH.J. Lu2020-10-131-6/+6
* Add support for Intel TDX instructions.Cui,Lili2020-09-241-4058/+4106
* Enable support to Intel Keylocker instructionsTerry Guo2020-09-231-3995/+4141
* x86: Add {disp16} pseudo prefixH.J. Lu2020-07-301-10/+22
* x86: Add support for Intel AMX instructionsLili Cui2020-07-101-14093/+14295
* x86: FMA4 scalar insns ignore VEX.LJan Beulich2020-07-081-16/+16
* x86: Add SwapSourcesH.J. Lu2020-07-021-3982/+3982
* x86: Correct xsusldtrk mnemonicH.J. Lu2020-06-141-1/+1
* Add support for intel TSXLDTRK instructions$Cui,Lili2020-04-071-3980/+4004
* Add support for intel SERIALIZE instructionLiliCui2020-04-021-3979/+3991
* x86: use template for AVX512 integer comparison insnsJan Beulich2020-03-091-32/+32
* x86: use template for XOP integer comparison, shift, and rotate insnsJan Beulich2020-03-091-168/+168
* x86: use template for AVX/AVX512 floating point comparison insnsJan Beulich2020-03-091-3381/+4277
* x86: use template for SSE floating point comparison insnsJan Beulich2020-03-091-144/+144
* x86: allow opcode templates to be templatedJan Beulich2020-03-091-15/+15
* x86: reduce amount of various VCVT* templatesJan Beulich2020-03-061-207/+65
* x86: drop/replace IgnoreSizeJan Beulich2020-03-061-903/+903
* x86: don't accept FI{LD,STP,STTP}LL in Intel syntax modeJan Beulich2020-03-061-6/+6
* x86: replace NoRex64 on VEX-encoded insnsJan Beulich2020-03-061-25/+25
* x86: drop Rex64 attributeJan Beulich2020-03-061-6576/+6576
* x86: add missing IgnoreSizeJan Beulich2020-03-061-18/+30
* x86: refine TPAUSE and UMWAITJan Beulich2020-03-061-6/+38
* x86: support VMGEXITJan Beulich2020-03-041-3929/+3941
* x86: Replace IgnoreSize/DefaultSize with MnemonicSizeH.J. Lu2020-03-031-10851/+10851
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