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path: root/opcodes/i386-tbl.h
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* X86: Remove the .s suffix from EVEX vpextrwH.J. Lu2016-11-091-1/+1
* X86: Merge AVX512F vmovqH.J. Lu2016-11-091-73/+9
* Enable Intel AVX512_4VNNIW instructionsIgor Tsimbalist2016-11-021-5207/+5321
* Enable Intel AVX512_4FMAPS instructionsIgor Tsimbalist2016-11-021-10432/+10584
* X86: Remove pcommit instructionH.J. Lu2016-10-211-5230/+5217
* X86: Add ptwrite instructionH.J. Lu2016-08-241-5199/+5212
* x86: allow suffix-less movzw and 64-bit movzbJan Beulich2016-07-011-68/+4
* x86: remove stray instruction attributesJan Beulich2016-07-011-44/+44
* x86/Intel: fix operand checking for MOVSDJan Beulich2016-07-011-2/+2
* Handle indirect branches for AMD64 and Intel64H.J. Lu2016-06-031-2/+28
* Update x86 CPU_XXX_FLAGS handlingH.J. Lu2016-05-271-5201/+5201
* Replace CpuAMD64/CpuIntel64 with AMD64/Intel64H.J. Lu2016-05-271-10402/+10402
* Correct CpuMax in i386-opc.hH.J. Lu2016-05-271-2/+2
* Enable Intel RDPID instruction.Alexander Fomin2016-05-101-5199/+5225
* Copyright update for binutilsAlan Modra2016-01-011-1/+1
* Implement Intel OSPKE instructionsH.J. Lu2015-12-091-5197/+5223
* Add support for monitorx/mwaitx instructionsAmit Pawar2015-06-301-5191/+5293
* x86/Intel: fix i386_optab[] for vcvt{,u}si2s{d,s}Jan Beulich2015-06-011-6/+6
* x86/Intel: accept mandated operand order for vcvt{,u}si2s{d,s}Jan Beulich2015-06-011-0/+132
* Remove Disp32 from AMD64 direct call/jmpH.J. Lu2015-05-181-2/+2
* Support AMD64/Intel ISAs in assembler/disassemblerH.J. Lu2015-05-151-5183/+5209
* Remove Disp16|Disp32 from 64-bit direct branchesH.J. Lu2015-05-111-3/+16
* Add Intel MCU support to opcodesH.J. Lu2015-05-111-5647/+5647
* Add znver1 processorGanesh Gopalasubramanian2015-03-171-5181/+5194
* ChangeLog rotatation and copyright year updateAlan Modra2015-01-021-1/+1
* Add AVX512VBMI instructionsIlya Tocar2014-11-171-5337/+5565
* Add AVX512IFMA instructionsIlya Tocar2014-11-171-5407/+5521
* Add pcommit instructionIlya Tocar2014-11-171-5162/+10337
* Add clwb instructionIlya Tocar2014-11-171-5161/+5173
* Add AVX512DQ instructions and their AVX512VL variants.Ilya Tocar2014-07-221-5726/+8831
* Add support for AVX512BW instructions and their AVX512VL versions.Ilya Tocar2014-07-221-5048/+10952
* Add support for AVX512VL versions of AVX512CD instructions.Ilya Tocar2014-07-221-0/+180
* Add support for AVX512VL. Add AVX512VL versions of AVX512F instructions.Ilya Tocar2014-07-221-4178/+19085
* Add support for Intel SGX instructionsIlya Tocar2014-04-041-3757/+3781
* Fix memory size for gather/scatter instructionsIlya Tocar2014-03-201-8/+8
* Update copyright yearsAlan Modra2014-03-051-2/+1
* Remove bogus vcvtps2ph variant.Ilya Tocar2014-02-251-18/+0
* Add support for CPUID PREFETCHWT1Ilya Tocar2014-02-211-3759/+3759
* Change cpu for vptestnmd and vptestnmq instructions.Ilya Tocar2014-02-201-32/+32
* Don't output trailing spaceH.J. Lu2014-02-191-41582/+41582
* Add clflushopt, xsaves, xsavec, xrstorsIlya Tocar2014-02-121-3752/+3836
* Only allow 32-bit/64-bit registers for bndcl/bndcu/bndcnH.J. Lu2013-10-121-14/+59
* opcodes/Jan Beulich2013-10-081-17/+17
* Add Size64 to movq/vmovq with Reg64 operandH.J. Lu2013-09-301-8/+8
* Add Intel AVX-512 supportH.J. Lu2013-07-261-14774/+37062
* Support Intel SHAH.J. Lu2013-07-251-2690/+2808
* Support Intel MPXH.J. Lu2013-07-241-9818/+9961
* Replace Xmmword with Qword on cvttps2piH.J. Lu2013-07-081-2/+2
* gas/testsuite/Jan Beulich2013-04-081-13/+2
* Add RegRex64 to rizH.J. Lu2013-03-021-4/+4
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