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path: root/opcodes/i386-tbl.h
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* x86: Accept Intel64 only instruction by defaultH.J. Lu2020-02-101-3925/+3925
* x86: VCVTNEPS2BF16{X,Y} should permit broadcastingJan Beulich2020-01-211-6/+6
* x86: Add {vex} pseudo prefixH.J. Lu2020-01-171-0/+12
* x86: add a few more missing VexWIGJan Beulich2020-01-161-4/+4
* x86: VPEXTRQ/VPINSRQ are unavailable outside of 64-bit modeJan Beulich2020-01-161-12/+12
* x86: SYSENTER/SYSEXIT are unavailable in 64-bit mode on AMDJan Beulich2020-01-091-2/+26
* Update year range in copyright notice of binutils filesAlan Modra2020-01-011-1/+1
* x86: consolidate Disp<NN> handling a littleJan Beulich2019-12-271-102/+88
* x86-64: accept 64-bit LFS/LGS/LSS forms with suffix or operand size specifierJan Beulich2019-12-041-3/+3
* x86: drop some stray/bogus DefaultSizeJan Beulich2019-12-041-5/+5
* x86: drop redundant SYSCALL/SYSRET templatesJan Beulich2019-11-141-24/+0
* x86: fold individual Jump* attributes into a single Jump oneJan Beulich2019-11-141-14843/+10922
* x86: make JumpAbsolute an insn attributeJan Beulich2019-11-141-26403/+26403
* x86: make AnySize an insn attributeJan Beulich2019-11-141-14458/+14458
* x86: fold EsSeg into IsStringJan Beulich2019-11-121-11187/+11187
* x86: eliminate ImmExt abuseJan Beulich2019-11-121-65/+145
* x86: introduce operand type "instance"Jan Beulich2019-11-121-14078/+14078
* i386: Only check suffix in instruction mnemonicH.J. Lu2019-11-081-2/+2
* x86: convert RegMask and RegBND from bitfield to enumeratorJan Beulich2019-11-081-14449/+14449
* x86: convert RegSIMD and RegMMX from bitfield to enumeratorJan Beulich2019-11-081-18968/+18968
* x86: convert Control/Debug/Test from bitfield to enumeratorJan Beulich2019-11-081-13847/+13847
* x86: convert SReg from bitfield to enumeratorJan Beulich2019-11-081-13720/+13720
* x86: support further AMD Zen2 instructionsJan Beulich2019-11-071-3913/+3939
* x86/Intel: drop IgnoreSize from operand-less MOVSD/CMPSD againJan Beulich2019-11-071-2/+2
* x86: slightly rearrange struct insn_templateJan Beulich2019-10-301-3912/+3912
* x86: drop stray WJan Beulich2019-10-301-12/+12
* x86/Intel: correct MOVSD and CMPSD handlingJan Beulich2019-10-071-8/+8
* x86-64: fix handling of PUSH/POP of segment registerJan Beulich2019-09-201-2/+28
* x86: drop stray FloatMFJan Beulich2019-08-071-7/+7
* x86: make RegMem an opcode modifierJan Beulich2019-07-161-16396/+20307
* x86: fold SReg{2,3}Jan Beulich2019-07-161-23782/+13834
* x86: drop Vec_Imm4Jan Beulich2019-07-011-9919/+9919
* x86: limit ImmExt abuseJan Beulich2019-07-011-84/+84
* x86: optimize AND/OR with twice the same registerJan Beulich2019-07-011-2/+2
* x86-64: optimize certain commutative VEX-encoded insnsJan Beulich2019-07-011-167/+167
* x86: optimize EVEX packed integer logical instructionsJan Beulich2019-07-011-4/+4
* x86: add missing pseudo ops for VPCLMULQDQ ISA extensionJan Beulich2019-07-011-0/+152
* x86: drop bogus Disp8MemShift attributesJan Beulich2019-07-011-3/+3
* x86: fix (dis)assembly of certain SSE2 insns in 16-bit modeJan Beulich2019-06-251-1/+1
* x86-64: also optimize ANDQ with immediate fitting in 7 bitsJan Beulich2019-06-251-1/+1
* Enable Intel AVX512_VP2INTERSECT insnH.J. Lu2019-06-041-3956/+3994
* Add support for Intel ENQCMD[S] instructionsH.J. Lu2019-06-041-3901/+3965
* x86: Add CheckRegSize to AVX512_BF16 instructions with Disp8ShiftVLH.J. Lu2019-05-281-2/+2
* x86: Consolidate AVX512 BF16 entries in i386-opc.tblH.J. Lu2019-04-081-260/+22
* x86: Support Intel AVX512 BF16Xuepeng Guo2019-04-051-3949/+4305
* x86: Optimize EVEX vector load/store instructionsH.J. Lu2019-03-181-6/+6
* Update year range in copyright notice of binutils filesAlan Modra2019-01-011-1/+1
* x86: adjust {,E}VEX.W handling for PEXTR* / PINSR*Jan Beulich2018-11-061-9/+9
* x86: adjust {,E}VEX.W handling outside of 64-bit modeJan Beulich2018-11-061-16/+16
* x86: fix various non-LIG templatesJan Beulich2018-11-061-43/+43
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