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* Enhancement for avx-vnni patchCui,Lili2020-10-161-3/+3
* x86: Support Intel AVX VNNIH.J. Lu2020-10-141-0/+6
* x86: Add support for Intel HRESET instructionLili Cui2020-10-141-0/+3
* x86: Support Intel UINTRLili Cui2020-10-141-0/+3
* x86: Rename VexOpcode to OpcodePrefixH.J. Lu2020-10-131-2/+12
* Add support for Intel TDX instructions.Cui,Lili2020-09-241-0/+3
* Enable support to Intel Keylocker instructionsTerry Guo2020-09-231-0/+6
* x86: Add {disp16} pseudo prefixH.J. Lu2020-07-301-0/+12
* x86: Add support for Intel AMX instructionsLili Cui2020-07-101-1/+15
* x86: Add SwapSourcesH.J. Lu2020-07-021-0/+4
* x86: Rename VecSIB to SIB for Intel AMXH.J. Lu2020-06-261-6/+6
* x86: restrict use of register aliasesJan Beulich2020-06-081-1/+1
* Add support for intel TSXLDTRK instructions$Cui,Lili2020-04-071-0/+3
* Add support for intel SERIALIZE instructionLiliCui2020-04-021-0/+3
* x86: drop Rex64 attributeJan Beulich2020-03-061-3/+0
* x86: support VMGEXITJan Beulich2020-03-041-0/+3
* x86: Replace IgnoreSize/DefaultSize with MnemonicSizeH.J. Lu2020-03-031-4/+4
* x86: Remove CpuABM and add CpuPOPCNTH.J. Lu2020-02-171-6/+6
* x86: drop ShortForm attributeJan Beulich2020-02-111-3/+0
* x86: Accept Intel64 only instruction by defaultH.J. Lu2020-02-101-6/+11
* Update year range in copyright notice of binutils filesAlan Modra2020-01-011-1/+1
* x86: fold individual Jump* attributes into a single Jump oneJan Beulich2019-11-141-11/+8
* x86: make JumpAbsolute an insn attributeJan Beulich2019-11-141-3/+3
* x86: make AnySize an insn attributeJan Beulich2019-11-141-5/+4
* x86: fold EsSeg into IsStringJan Beulich2019-11-121-6/+8
* x86: eliminate ImmExt abuseJan Beulich2019-11-121-2/+3
* x86: introduce operand type "instance"Jan Beulich2019-11-121-11/+14
* x86: convert RegMask and RegBND from bitfield to enumeratorJan Beulich2019-11-081-7/+2
* x86: convert RegSIMD and RegMMX from bitfield to enumeratorJan Beulich2019-11-081-6/+2
* x86: convert Control/Debug/Test from bitfield to enumeratorJan Beulich2019-11-081-9/+3
* x86: convert SReg from bitfield to enumeratorJan Beulich2019-11-081-3/+1
* x86: introduce operand type "class"Jan Beulich2019-11-081-4/+13
* x86: support further AMD Zen2 instructionsJan Beulich2019-11-071-0/+6
* x86: slightly rearrange struct insn_templateJan Beulich2019-10-301-4/+4
* x86: drop stray WJan Beulich2019-10-301-1/+3
* x86: drop stale Mem enumeratorJan Beulich2019-07-171-3/+1
* x86: make RegMem an opcode modifierJan Beulich2019-07-161-7/+6
* x86: fold SReg{2,3}Jan Beulich2019-07-161-6/+3
* x86: drop Vec_Imm4Jan Beulich2019-07-011-4/+0
* Enable Intel AVX512_VP2INTERSECT insnH.J. Lu2019-06-041-0/+3
* Add support for Intel ENQCMD[S] instructionsH.J. Lu2019-06-041-0/+3
* x86: Support Intel AVX512 BF16Xuepeng Guo2019-04-051-0/+3
* Update year range in copyright notice of binutils filesAlan Modra2019-01-011-1/+1
* x86: fold Size{16,32,64} template attributesJan Beulich2018-10-101-6/+5
* x86: Support VEX/EVEX WIG encodingH.J. Lu2018-09-141-0/+2
* x86: use D attribute also for SIMD templatesJan Beulich2018-09-131-0/+2
* x86: Add CpuCMOV and CpuFXSRH.J. Lu2018-08-111-0/+6
* x86: fold RegEip/RegRip and RegEiz/RegRizJan Beulich2018-08-061-4/+2
* x86: drop "mem" operand type attributeJan Beulich2018-08-031-1/+0
* x86: fold various AVX512 templates with so far differing Masking attributesJan Beulich2018-07-311-2/+2
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