summaryrefslogtreecommitdiff
path: root/opcodes/i386-dis.c
Commit message (Expand)AuthorAgeFilesLines
...
* libopcodes: extend the styling within the i386 disassemblerAndrew Burgess2022-06-081-137/+286
* opcodes/i386: remove trailing whitespace from insns with zero operandsAndrew Burgess2022-05-271-5/+22
* x86/Intel: adjust representation of embedded rounding / SAEJan Beulich2022-05-271-0/+17
* x86/Intel: adjust representation of embedded broadcastJan Beulich2022-05-271-4/+11
* x86: shrink op_riprelJan Beulich2022-05-181-18/+12
* Fix multiple ubsan warnings in i386-dis.cAlan Modra2022-05-071-13/+13
* x86: correct and simplify NOP disassemblyJan Beulich2022-04-191-21/+9
* opcodes/i386: partially implement disassembler style supportAndrew Burgess2022-04-041-23/+40
* x86: drop L1OM special case from disassemblerJan Beulich2022-03-241-6/+2
* x86: Add has_sib to struct instr_infoH.J. Lu2022-02-151-8/+9
* x86: adjust struct instr_info field typesJan Beulich2022-01-171-36/+39
* x86: drop index16 fieldJan Beulich2022-01-171-5/+3
* x86: drop most Intel syntax register name arraysJan Beulich2022-01-171-230/+119
* x86: fold variables in memory operand index handlingJan Beulich2022-01-171-19/+15
* x86: constify disassembler static dataJan Beulich2022-01-171-58/+58
* x86: drop ymmxmm_modeJan Beulich2022-01-141-16/+0
* x86: share yet more VEX table entries with EVEX decodingJan Beulich2022-01-141-73/+53
* x86: record further wrong uses of EVEX.bJan Beulich2022-01-141-0/+8
* x86: reduce AVX512 FP set of insns decoded through vex_w_table[]Jan Beulich2022-01-141-41/+1
* x86: reduce AVX512-FP16 set of insns decoded through vex_w_table[]Jan Beulich2022-01-141-33/+39
* opcodes: Make i386-dis.c thread-safeVladimir Mezentsev2022-01-051-1738/+1774
* Update year range in copyright notice of binutils filesAlan Modra2022-01-021-1/+1
* x86: Terminate mnemonicendp in swap_operand()Vladimir Mezentsev2021-12-171-0/+1
* x86: Print {bad} on invalid broadcast in OP_E_memoryCui,Lili2021-09-281-74/+81
* x86: Put back 3 aborts in OP_E_memoryH.J. Lu2021-08-191-3/+3
* x86: Avoid abort on invalid broadcastH.J. Lu2021-08-191-4/+4
* [PATCH 1/2] Enable Intel AVX512_FP16 instructionsCui,Lili2021-08-051-27/+225
* x86: express unduly set rounding control bits in disassemblyJan Beulich2021-07-231-37/+53
* x86: drop dq{b,d}_modeJan Beulich2021-07-221-30/+13
* x86: drop vex_scalar_w_dq_modeJan Beulich2021-07-221-28/+18
* x86: drop xmm_m{b,w,d,q}_modeJan Beulich2021-07-221-127/+54
* x86: fold duplicate vector register printing codeJan Beulich2021-07-221-74/+33
* x86: drop vex_mode and vex_scalar_modeJan Beulich2021-07-221-11/+7
* x86: correct EVEX.V' handling outside of 64-bit modeJan Beulich2021-07-221-4/+16
* x86: fold duplicate code in MOVSXD_Fixup()Jan Beulich2021-07-221-16/+10
* x86: fold duplicate register printing codeJan Beulich2021-07-221-105/+14
* x86-64: properly bounds-check %bnd<N> in OP_G()Jan Beulich2021-07-221-1/+1
* x86-64: generalize OP_G()'s EVEX.R' handlingJan Beulich2021-07-221-1/+8
* x86: correct VCVT{,U}SI2SD rounding mode handlingJan Beulich2021-07-221-3/+1
* x86: drop OP_Mask()Jan Beulich2021-07-221-22/+2
* x86: Add int1 as one byte opcode 0xf1H.J. Lu2021-07-141-1/+1
* Use bool in opcodesAlan Modra2021-03-311-4/+4
* x86: flag bad S/G insn operand combinationsJan Beulich2021-03-251-14/+70
* x86: flag as bad AVX512 insns with EVEX.z set but EVEX.aaa clearJan Beulich2021-03-251-0/+7
* Add startswith function and use it instead of CONST_STRNEQ.Martin Liska2021-03-221-12/+12
* Re: x86: correct decoding of nop/reserved space (0f18 ... 0x1f)Alan Modra2021-03-121-1/+1
* x86: re-order logic in OP_XMM()Jan Beulich2021-03-111-35/+31
* x86: drop a few redundant EVEX-related checksJan Beulich2021-03-111-4/+3
* x86: remove stray uses of xmmq_modeJan Beulich2021-03-111-4/+1
* x86/Intel: correct AVX512 S/G disassemblyJan Beulich2021-03-101-70/+12
View Lorry Controller Status