| Commit message (Expand) | Author | Age | Files | Lines |
|---|
| * | x86: express unduly set rounding control bits in disassembly | Jan Beulich | 2021-07-23 | 1 | -37/+53 |
| * | x86: drop dq{b,d}_mode | Jan Beulich | 2021-07-22 | 1 | -30/+13 |
| * | x86: drop vex_scalar_w_dq_mode | Jan Beulich | 2021-07-22 | 1 | -28/+18 |
| * | x86: drop xmm_m{b,w,d,q}_mode | Jan Beulich | 2021-07-22 | 1 | -127/+54 |
| * | x86: fold duplicate vector register printing code | Jan Beulich | 2021-07-22 | 1 | -74/+33 |
| * | x86: drop vex_mode and vex_scalar_mode | Jan Beulich | 2021-07-22 | 1 | -11/+7 |
| * | x86: correct EVEX.V' handling outside of 64-bit mode | Jan Beulich | 2021-07-22 | 1 | -4/+16 |
| * | x86: fold duplicate code in MOVSXD_Fixup() | Jan Beulich | 2021-07-22 | 1 | -16/+10 |
| * | x86: fold duplicate register printing code | Jan Beulich | 2021-07-22 | 1 | -105/+14 |
| * | x86-64: properly bounds-check %bnd<N> in OP_G() | Jan Beulich | 2021-07-22 | 1 | -1/+1 |
| * | x86-64: generalize OP_G()'s EVEX.R' handling | Jan Beulich | 2021-07-22 | 1 | -1/+8 |
| * | x86: correct VCVT{,U}SI2SD rounding mode handling | Jan Beulich | 2021-07-22 | 1 | -3/+1 |
| * | x86: drop OP_Mask() | Jan Beulich | 2021-07-22 | 1 | -22/+2 |
| * | x86: Add int1 as one byte opcode 0xf1 | H.J. Lu | 2021-07-14 | 1 | -1/+1 |
| * | Use bool in opcodes | Alan Modra | 2021-03-31 | 1 | -4/+4 |
| * | x86: flag bad S/G insn operand combinations | Jan Beulich | 2021-03-25 | 1 | -14/+70 |
| * | x86: flag as bad AVX512 insns with EVEX.z set but EVEX.aaa clear | Jan Beulich | 2021-03-25 | 1 | -0/+7 |
| * | Add startswith function and use it instead of CONST_STRNEQ. | Martin Liska | 2021-03-22 | 1 | -12/+12 |
| * | Re: x86: correct decoding of nop/reserved space (0f18 ... 0x1f) | Alan Modra | 2021-03-12 | 1 | -1/+1 |
| * | x86: re-order logic in OP_XMM() | Jan Beulich | 2021-03-11 | 1 | -35/+31 |
| * | x86: drop a few redundant EVEX-related checks | Jan Beulich | 2021-03-11 | 1 | -4/+3 |
| * | x86: remove stray uses of xmmq_mode | Jan Beulich | 2021-03-11 | 1 | -4/+1 |
| * | x86/Intel: correct AVX512 S/G disassembly | Jan Beulich | 2021-03-10 | 1 | -70/+12 |
| * | x86: re-arrange enumerator and table entry order | Jan Beulich | 2021-03-10 | 1 | -77/+79 |
| * | x86: reuse further VEX entries for EVEX | Jan Beulich | 2021-03-10 | 1 | -17/+11 |
| * | x86: reuse VEX entries for EVEX vperm{q,pd} | Jan Beulich | 2021-03-10 | 1 | -4/+2 |
| * | x86: re-arrange order of decode for various EVEX opcodes | Jan Beulich | 2021-03-10 | 1 | -79/+42 |
| * | x86: re-arrange order of decode for various mask reg opcodes | Jan Beulich | 2021-03-10 | 1 | -600/+328 |
| * | x86: re-arrange order of decode for various VEX opcodes | Jan Beulich | 2021-03-10 | 1 | -154/+70 |
| * | x86: re-arrange order of decode for various legacy opcodes | Jan Beulich | 2021-03-10 | 1 | -70/+28 |
| * | x86: correct decoding of nop/reserved space (0f18 ... 0x1f) | Jan Beulich | 2021-03-10 | 1 | -48/+45 |
| * | x86-64: make SYSEXIT handling similar to SYSRET's | Jan Beulich | 2021-03-09 | 1 | -1/+1 |
| * | Update year range in copyright notice of binutils files | Alan Modra | 2021-01-01 | 1 | -1/+1 |
| * | x86: Do not dump DS/CS segment overrides for branch hints | Borislav Petkov | 2020-11-29 | 1 | -2/+11 |
| * | x86: Ignore CS/DS/ES/SS segment-override prefixes in 64-bit mode | Borislav Petkov | 2020-11-14 | 1 | -5/+20 |
| * | Change avxvnni disassembler output from {vex3} to {vex} | Cui,Lili | 2020-10-26 | 1 | -1/+0 |
| * | Add AMD znver3 processor support | Ganesh Gopalasubramanian | 2020-10-20 | 1 | -0/+41 |
| * | x86: Support Intel AVX VNNI | H.J. Lu | 2020-10-14 | 1 | -6/+37 |
| * | x86: Add support for Intel HRESET instruction | Lili Cui | 2020-10-14 | 1 | -1/+24 |
| * | x86: Support Intel UINTR | Lili Cui | 2020-10-14 | 1 | -6/+69 |
| * | x86-64: Always display suffix for %LQ in 64bit | H.J. Lu | 2020-10-05 | 1 | -1/+1 |
| * | x86: Clear modrm if not needed | H.J. Lu | 2020-10-05 | 1 | -4/+8 |
| * | Put together MOD_VEX_0F38* in i386-dis.c, | Cui,Lili | 2020-09-25 | 1 | -62/+62 |
| * | Add support for Intel TDX instructions. | Cui,Lili | 2020-09-24 | 1 | -4/+61 |
| * | Enable support to Intel Keylocker instructions | Terry Guo | 2020-09-23 | 1 | -7/+100 |
| * | ubsan: i386-dis.c | Alan Modra | 2020-09-02 | 1 | -13/+13 |
| * | Revert "x86: Don't display eiz with no scale" | Jan Beulich | 2020-07-21 | 1 | -1/+1 |
| * | x86: Don't display eiz with no scale | H.J. Lu | 2020-07-15 | 1 | -1/+1 |
| * | x86: move putop() case labels to restore alphabetic sorting | Jan Beulich | 2020-07-15 | 1 | -49/+48 |
| * | x86: make PUSH/POP disassembly uniform | Jan Beulich | 2020-07-15 | 1 | -30/+20 |
