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path: root/opcodes/i386-dis-evex.h
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* x86: honor VEX.W for VCVT{PH2PS,PS2PH}Jan Beulich2020-07-061-1/+1
* x86: drop EVEX table entries that can be served by VEX onesJan Beulich2020-07-061-80/+80
* x86: utilize X macro in EVEX decodingJan Beulich2020-06-091-12/+12
* i386: Break i386-dis-evex.h into small filesH.J. Lu2019-06-211-3467/+0
* i386: Check vector length for EVEX broadcast instructionsH.J. Lu2019-06-191-10/+80
* i386: Check vector length for vshufXXX/vinsertXXX/vextractXXXH.J. Lu2019-06-171-12/+96
* i386: Check vector length for EVEX vextractfXX and vinsertfXXH.J. Lu2019-06-051-8/+64
* Enable Intel AVX512_VP2INTERSECT insnH.J. Lu2019-06-041-1/+13
* x86: Support Intel AVX512 BF16Xuepeng Guo2019-04-051-2/+18
* x86: correctly handle VPBROADCASTD with EVEX.W set outside of 64-bit modeJan Beulich2018-11-061-1/+1
* x86: correctly handle VMOVD with EVEX.W set outside of 64-bit modeJan Beulich2018-11-061-12/+2
* x86: adjust {,E}VEX.W handling for PEXTR* / PINSR*Jan Beulich2018-11-061-12/+2
* x86: Set EVex=2 on EVEX.128 only vmovd and vmovqH.J. Lu2018-09-171-4/+26
* x86: Handle unsupported static rounding in vcvt[u]si2sd in 32-bit modeH.J. Lu2018-09-141-2/+2
* x86: Properly decode EVEX.W in vcvt[u]si2s[sd] in 32-bit modeH.J. Lu2018-09-141-4/+4
* x86-64: correct AVX512F vcvtsi2s{d,s} handlingJan Beulich2018-07-241-8/+8
* x86: add support for AVX-512 VPCMP*{B,W} pseudo-opsJan Beulich2017-11-141-4/+4
* Enable Intel AVX512_BITALG instructions.Igor Tsimbalist2017-10-231-2/+19
* Enable Intel AVX512_VNNI instructions.Igor Tsimbalist2017-10-231-4/+16
* Enable Intel VPCLMULQDQ instruction.Igor Tsimbalist2017-10-231-1/+7
* Enable Intel VAES instructions.Igor Tsimbalist2017-10-231-4/+29
* Enable Intel GFNI instructions.Igor Tsimbalist2017-10-231-3/+31
* Enable Intel AVX512_VBMI2 instructions.Igor Tsimbalist2017-10-231-10/+120
* Enable Intel AVX512_VPOPCNTDQ instructionsIgor Tsimbalist2017-01-121-1/+12
* X86: Remove the .s suffix from EVEX vpextrwH.J. Lu2016-11-091-1/+1
* Enable Intel AVX512_4VNNIW instructionsIgor Tsimbalist2016-11-021-2/+16
* Enable Intel AVX512_4FMAPS instructionsIgor Tsimbalist2016-11-021-0/+4
* Fix memory operand size for vcvtt?ps2u?qq instructionsH.J. Lu2015-07-221-4/+4
* x86: disambiguate disassembly of certain AVX512 insnsJan Beulich2015-04-231-9/+9
* x86: Use individual prefix control for each opcode.Ilya Tocar2015-04-061-472/+472
* Add AVX512VBMI instructionsIlya Tocar2014-11-171-4/+15
* Add AVX512IFMA instructionsIlya Tocar2014-11-171-2/+14
* Add AVX512DQ instructions and their AVX512VL variants.Ilya Tocar2014-07-221-26/+215
* Add support for AVX512BW instructions and their AVX512VL versions.Ilya Tocar2014-07-221-76/+636
* Fix disasm of vmovsd/vmovss with different length values.Ilya Tocar2014-07-081-2/+2
* Fix memory size for gather/scatter instructionsIlya Tocar2014-03-201-8/+8
* Remove PREFIX_EVEX_0F3A3E and PREFIX_EVEX_0F3A3FH.J. Lu2013-08-191-14/+2
* Add Intel AVX-512 supportH.J. Lu2013-07-261-0/+3115
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