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path: root/opcodes/i386-dis-evex.h
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* Support Intel AVX-IFMAHongyu Wang2022-11-021-2/+2
* x86: emit {evex} prefix when disassembling ambiguous AVX512VL insnsJan Beulich2022-10-241-87/+87
* x86: fold AVX512-VNNI disassembler entries with AVX-VNNI onesJan Beulich2022-10-171-2/+2
* x86: share yet more VEX table entries with EVEX decodingJan Beulich2022-01-141-16/+16
* x86: consistently use scalar_mode for AVX512-FP16 scalar insnsJan Beulich2022-01-141-16/+16
* x86: reduce AVX512 FP set of insns decoded through vex_w_table[]Jan Beulich2022-01-141-4/+4
* x86: reduce AVX512-FP16 set of insns decoded through vex_w_table[]Jan Beulich2022-01-141-5/+5
* [PATCH 1/2] Enable Intel AVX512_FP16 instructionsCui,Lili2021-08-051-13/+595
* x86: drop vex_scalar_w_dq_modeJan Beulich2021-07-221-21/+21
* x86: drop OP_Mask()Jan Beulich2021-07-221-11/+11
* x86: flag bad S/G insn operand combinationsJan Beulich2021-03-251-2/+2
* x86/Intel: correct AVX512 S/G disassemblyJan Beulich2021-03-101-4/+4
* x86: reuse further VEX entries for EVEXJan Beulich2021-03-101-10/+10
* x86: reuse VEX entries for EVEX vperm{q,pd}Jan Beulich2021-03-101-2/+2
* x86: re-arrange order of decode for various EVEX opcodesJan Beulich2021-03-101-17/+17
* x86: drop Rdq, Rd, and MaskRJan Beulich2020-07-141-1/+1
* x86: simplify decode of opcodes valid with (embedded) 66 prefix onlyJan Beulich2020-07-141-217/+217
* x86: drop further EVEX table entries that can be served by VEX onesJan Beulich2020-07-141-4/+4
* x86: drop EVEX table entries that can be made served by VEX onesJan Beulich2020-07-061-15/+15
* x86: honor VEX.W for VCVT{PH2PS,PS2PH}Jan Beulich2020-07-061-1/+1
* x86: drop EVEX table entries that can be served by VEX onesJan Beulich2020-07-061-80/+80
* x86: utilize X macro in EVEX decodingJan Beulich2020-06-091-12/+12
* i386: Break i386-dis-evex.h into small filesH.J. Lu2019-06-211-3467/+0
* i386: Check vector length for EVEX broadcast instructionsH.J. Lu2019-06-191-10/+80
* i386: Check vector length for vshufXXX/vinsertXXX/vextractXXXH.J. Lu2019-06-171-12/+96
* i386: Check vector length for EVEX vextractfXX and vinsertfXXH.J. Lu2019-06-051-8/+64
* Enable Intel AVX512_VP2INTERSECT insnH.J. Lu2019-06-041-1/+13
* x86: Support Intel AVX512 BF16Xuepeng Guo2019-04-051-2/+18
* x86: correctly handle VPBROADCASTD with EVEX.W set outside of 64-bit modeJan Beulich2018-11-061-1/+1
* x86: correctly handle VMOVD with EVEX.W set outside of 64-bit modeJan Beulich2018-11-061-12/+2
* x86: adjust {,E}VEX.W handling for PEXTR* / PINSR*Jan Beulich2018-11-061-12/+2
* x86: Set EVex=2 on EVEX.128 only vmovd and vmovqH.J. Lu2018-09-171-4/+26
* x86: Handle unsupported static rounding in vcvt[u]si2sd in 32-bit modeH.J. Lu2018-09-141-2/+2
* x86: Properly decode EVEX.W in vcvt[u]si2s[sd] in 32-bit modeH.J. Lu2018-09-141-4/+4
* x86-64: correct AVX512F vcvtsi2s{d,s} handlingJan Beulich2018-07-241-8/+8
* x86: add support for AVX-512 VPCMP*{B,W} pseudo-opsJan Beulich2017-11-141-4/+4
* Enable Intel AVX512_BITALG instructions.Igor Tsimbalist2017-10-231-2/+19
* Enable Intel AVX512_VNNI instructions.Igor Tsimbalist2017-10-231-4/+16
* Enable Intel VPCLMULQDQ instruction.Igor Tsimbalist2017-10-231-1/+7
* Enable Intel VAES instructions.Igor Tsimbalist2017-10-231-4/+29
* Enable Intel GFNI instructions.Igor Tsimbalist2017-10-231-3/+31
* Enable Intel AVX512_VBMI2 instructions.Igor Tsimbalist2017-10-231-10/+120
* Enable Intel AVX512_VPOPCNTDQ instructionsIgor Tsimbalist2017-01-121-1/+12
* X86: Remove the .s suffix from EVEX vpextrwH.J. Lu2016-11-091-1/+1
* Enable Intel AVX512_4VNNIW instructionsIgor Tsimbalist2016-11-021-2/+16
* Enable Intel AVX512_4FMAPS instructionsIgor Tsimbalist2016-11-021-0/+4
* Fix memory operand size for vcvtt?ps2u?qq instructionsH.J. Lu2015-07-221-4/+4
* x86: disambiguate disassembly of certain AVX512 insnsJan Beulich2015-04-231-9/+9
* x86: Use individual prefix control for each opcode.Ilya Tocar2015-04-061-472/+472
* Add AVX512VBMI instructionsIlya Tocar2014-11-171-4/+15
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